Prof. Dr. Robert Schmidt

Neural Data Science

Head of Chair

Address:
Ruhr-University Bochum
Faculty of Computer Science
Neural Data Science
Universitätsstr. 150
--D-44801 Bochum

Telephone: 0234 / 32-27300

Office Hours: By arrangement

E-Mail: robert.schmidt@rub.de

Courses



    • Prof. Dr.

    ROBERT SCHMIDT

    • Neural Data Science

    Ruhr-University Bochum
    Faculty of Computer Science
    Neural Data Science
    Universitätsstr. 150

    44801 Bochum

    Room:  NB 3.68

    Tel:      +49 (0)234 32-27300

    E-Mail: robert.schmidt@rub.de

    Office hours: By Arrangement

    Table of Contents

    Courses

    Publications

    2024

    [1]
    P. Mackensen, P. Staat, S. Roth, A. Sezgin, C. Paar, und V. Moonsamy, „Spatial-Domain Wireless Jamming with Reconfigurable Intelligent Surfaces“, 2024.
    [1]
    E. Puschner, T. Moos, S. Becker, C. Kison, A. Moradi, und C. Paar, „Red team vs. blue team: a real-world hardware trojan detection case study across four modern CMOS technology generations“, in Proceedings of the IEEE Symposium on Security and Privacy, San Francisco, Ca, 2023, Im Erscheinen.
    [2]
    C. Saatjohann, C. Paar, und S. Schinzel, „Practical (in)security of IoT and medical IT systems“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2023. doi: 10.13154/294-10522.
    [3]
    D. V. Bailey, M. Dürmuth, und C. Paar, „Securing knowledge-based authentication against online attackers“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2023. doi: 10.13154/294-10303.
    [4]
    J. Tobisch, C. Paar, und I. Verbauwhede, „Physical systems for integrity protection and authentication“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2023. doi: 10.13154/294-10347.
    [5]
    J. Tobisch u. a., „Remote inspection of adversary-controlled environments“, Nature communications, Bd. 14, Nr. 1, Okt. 2023, doi: 10.1038/s41467-023-42314-2.
    [6]
    S. Engels, C. Paar, und T. Güneysu, „Selected aspects of cryptographic engineering“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2023. doi: 10.13154/294-11055.
    [1]
    J. Speith, F. Schweins, M. Ender, M. Fyrbiak, A. May, und C. Paar, „How not to protect your IP: an industry-wide break of IEEE 1735“, in 2022 IEEE Symposium on Security and Privacy (SP), San Francisco, CA, 2022, S. 1067–1082. doi: 10.1109/SP46214.2022.9833605.
    [2]
    P. Staat, S. Mulzer, S. Roth, V. Moonsamy, A. Sezgin, und C. Paar, „IRShield: a countermeasure against adversarial physical-layer wireless sensing“, 2022.
    [3]
    P. Staat, K. Jansen, C. Zenger, H. Elders-Boll, und C. Paar, „Analog physical-layer relay attacks with application to bluetooth and phase-based ranging“, 2022.
    [4]
    P. Staat u. a., „IRShield: a countermeasure against adversarial physical-layer wireless sensing“, in 2022 IEEE Symposium on Security and Privacy (SP), San Francisco, CA, 2022, S. 1526–1526. doi: 10.1109/SP46214.2022.9833676.
    [5]
    P. Staat, J. Tobisch, C. Zenger, und C. Paar, „Anti-tamper radio: system-level tamper detection for computing systems“, in 2022 IEEE Symposium on Security and Privacy (SP), San Francisco, CA, 2022, S. 1150–1164. doi: 10.1109/SP46214.2022.9833631.
    [6]
    M. Ender, N.-G. Leander, A. Moradi, und C. Paar, „A cautionary note on protecting Xilinx’ UltraScale(+) Bitstream encryption and authentication engine“, in Proceedings – 2022 IEEE 30th International Symposium on Field-Programmable Custom Computing Machines, New York, Juni 2022, Publiziert. doi: 10.1109/fccm53951.2022.9786118.
    [7]
    H. Elders-Boll, K. Jansen, C. Paar, P. Staat, und C. Zenger, „Analog physical-layer relay attacks with application to bluetooth and phase-based ranging“, in WiSec ’22 , an Antonio TX USA, Mai 2022, S. 60–72. doi: 10.1145/3507657.3528536.
    [8]
    C. Wiesen, C. Paar, R. Walendy, N. Rummel, und S. Becker, „The anatomy of hardware reverse engineering: : an exploration of human factors during problem solving“, ACM transactions on computer human interaction , Dez. 2022, Publiziert, doi: 10.1145/3577198.
    [9]
    T. Moos, A. Moradi, C. Paar, und F.-X. Standaert, „Physical security for next generation CMOS ICs“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2022. doi: 10.13154/294-9275.
    [10]
    G. Li u. a., „Reconfigurable intelligent surface for physical layer key generation: : constructive or destructive?“, IEEE wireless communications / Institute of Electrical and Electronics Engineers, Bd. 29, Nr. 4, S. 146–153, Mai 2022, doi: 10.1109/mwc.007.2100545.
    [11]
    C. Abate, C. Hrițcu, und C. Paar, „A formal framework for correct and secure compilation“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2022. doi: 10.13154/294-9870.
    [1]
    F. Stolz u. a., „LifeLine for FPGA protection: obfuscated cryptography for real-world security“, IACR transactions on cryptographic hardware and embedded systems, Bd. 2021, Nr. 4, S. 412–446, Aug. 2021, doi: 10.46586/tches.v2021.i4.412-446.
    [2]
    L. Azriel, J. Speith, N. Albartus, R. Ginosar, A. Mendelson, und C. Paar, „A survey of algorithmic methods in IC reverse engineering“, Journal of cryptographic engineering, Bd. 11, Nr. 3, S. 299–315, Juli 2021, doi: 10.1007/s13389-021-00268-5.
    [3]
    N. Albartus, C. Nasenberg, F. Stolz, M. Fyrbiak, C. Paar, und R. Tessier, „On the design and misuse of microcoded (embedded) processors – a cautionary note“, in Proceedings of the 30th USENIX Security Symposium, Online, 2021, S. 267–284. [Online]. Verfügbar unter: https://www.usenix.org/conference/usenixsecurity21/presentation/albartus
    [4]
    P. Zimmer, R. Weinreich, C. Zenger, A. Sezgin, und C. Paar, „Keys from the sky: a first exploration of physical-layer security using satellite links“, in ICC 2021 – IEEE International Conference on Communications, Montreal, Quebec, 2021, S. 300–306. doi: 10.1109/icc42927.2021.9500958.
    [5]
    P. Staat, H. Elders-Boll, M. Heinrichs, R. Kronberger, C. Zenger, und C. Paar, „Intelligent reflecting surface-assisted wireless key generation for low-entropy environments“, in 2021 IEEE 32nd Annual International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), Online, 2021, S. 745–751. doi: 10.1109/pimrc50174.2021.9569556.
    [6]
    E. Puschner u. a., „Listen to your heart: evaluation of the cardiologic ecosystem“, in ARES 2021, Vienna, Aug. 2021, Publiziert. doi: 10.1145/3465481.3465753.
    [7]
    P. Staat, J. Tobisch, C. Zenger, und C. Paar, „Anti-tamper radio: system-level tamper detection for computing systems“, 16. Dezember 2021.
    [8]
    P. Staat, H. Elders-Boll, M. Heinrichs, C. Zenger, und C. Paar, „Mirror mirror on the wall: wireless environment reconfiguration attacks based on fast software-controlled surfaces“, 2021.
    [9]
    C. Wiesen, C. Paar, und N. Rummel, „How do engineers analyze netlists? : Human problem-solving processes in hardware reverse engineering“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2021. doi: 10.13154/294-8490.
    [10]
    H. Elders-Boll, M. Heinrichs, C. Paar, P. Staat, und C. Zenger, „Mirror mirror on the wall: : wireless environment reconfiguration attacks based on fast software-controlled surfaces“, in Proceedings of the 2022 ACM on asia conference on computer and communications security, Nagasaki, Juli 2021, S. 208–221. doi: 10.1145/3488932.3497767.
    [11]
    S. Becker, C. Paar, N. Rummel, und R. Karr, „Human factors in hardware reverse engineering “, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2021. doi: 10.13154/294-9414.
    [1]
    S. Ghandali, T. Moos, A. Moradi, und C. Paar, „Side-channel hardware trojan for provably-secure SCA-protected implementations“, IEEE transactions on very large scale integration (VLSI) systems / Institute of Electrical and Electronics Engineers, Bd. 28, Nr. 6, S. 1435–1448, Apr. 2020, doi: 10.1109/tvlsi.2020.2982473.
    [2]
    M. Hoffmann, C. Paar, I. Verbauwhede, und E. Kiltz, „Security and subvertability of modern hardware: a journey through selected layers of hardware security“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2020. doi: 10.13154/294-7689.
    [3]
    N. Albartus, M. Hoffmann, S. Temme, L. Azriel, und C. Paar, „DANA universal dataflow analysis for gate-level netlist reverse engineering“, IACR transactions on cryptographic hardware and embedded systems, Bd. 2020, Nr. 4, S. 309–336, 2020, doi: 10.13154/tches.v2020.i4.309-336.
    [4]
    M. Ender, A. Moradi, und C. Paar, „The unpatchable silicon: a full break of the bitstream encryption of Xilinx 7-series FPGAs“, in Proceedings of the 29th USENIX Security Symposium, Online, 2020, S. 1803–1819. [Online]. Verfügbar unter: https://www.usenix.org/conference/usenixsecurity20/presentation/ender
    [5]
    M. Ender, A. Moradi, und C. Paar, „The unpatchable silicon: a full break of the bitstream encryption of Xilinx 7-series FPGAs“, 2020. [Online]. Verfügbar unter: https://www.usenix.org/system/files/sec20fall_ender_prepub.pdf
    [6]
    B. Richter, A. Moradi, T. Eisenbarth, C. Paar, und T. Güneysu, „Advanced side-channel measurement and testing“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2020. doi: 10.13154/294-8024.
    [7]
    B. Garmany, T. Holz, K. Rieck, und C. Paar, „MENTALESE: an architecture-agnostic analysis framework for binary executables“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2020. doi: 10.13154/294-8080.
    [8]
    M. Hoffmann, F. Schellenberg, und C. Paar, „ARMORY: fully automated and exhaustive fault simulation on ARM-M binaries“, IEEE transactions on information forensics and security / Institute of Electrical and Electronics Engineers, Bd. 16, S. 1058–1073, Sep. 2020, doi: 10.1109/tifs.2020.3027143.
    [9]
    M. Hoffmann und C. Paar, „Doppelganger obfuscation – exploring the defensive and offensive aspects of hardware camouflaging “, IACR transactions on cryptographic hardware and embedded systems, Bd. 2021, Nr. 1, S. 82–108, Dez. 2020, doi: 10.46586/tches.v2021.i1.82-108.
    [10]
    S. Becker, C. Wiesen, N. Albartus, N. Rummel, und C. Paar, „An exploratory study of hardware reverse engineering – technical and cognitive processes“, in Proceedings of the Sixteenth Symposium on Usable Privacy and Security (SOUPS 2020), Online, 2020, S. 285–300.
    [11]
    S. Engels, F. Schellenberg, und C. Paar, „SPFA : SFA on Multiple Persistent Faults“, in 2020 Workshop on Fault Detection and Tolerance in Cryptography (FDTC 2020), Online, 2020, S. 49–56. doi: 10.1109/fdtc51366.2020.00014.
    [12]
    J. Speith, S. Becker, M. Ender, E. Puschner, und C. Paar, „Hardware-Trojaner: die unsichtbare Gefahr“, Datenschutz und Datensicherheit, Bd. 44, Nr. 7, S. 446–450, Juni 2020, doi: 10.1007/s11623-020-1303-3.
    [13]
    P. Staat, K. Jansen, C. Zenger, und C. Paar, „Securing Phone as a Key against relay attacks“, in 18th escar Europe – The World’s Leading Automotive Cyber Security Conference, Online, Sep. 2020, S. 47–58. doi: 10.13154/294-7546.
    [14]
    J. Tobisch, C. Zenger, und C. Paar, „Electromagnetic enclosure PUF for tamper proofing commodity hardware and other applications“, gehalten auf der DATE20 Design Automation and Test in Europe Conference, Workshop W07 TRUDEVICE 2020, Online, 13. März 2020, Publiziert.
    [15]
    P. Staat, H. Elders-Boll, M. Heinrichs, R. Kronberger, C. Zenger, und C. Paar, „Intelligent reflecting surface-assisted wireless key generation for low-entropy environments“, 13. Oktober 2020. https://casa.rub.de/fileadmin/img/Publikationen_PDFs/2021_Intelligent_Reflecting_Surface-Assisted_Wireless_Key_Generation_for_Low-Entropy_Environments_Publication_ClusterofExcellence_CASA_Bochum.pdf
    [16]
    P. Zimmer, R. Weinreich, C. Zenger, A. Sezgin, und C. Paar, „Keys from the sky: a first exploration of physical-layer security using satellite links“, 14. Oktober 2020.
    [17]
    J. Tobisch, C. Zenger, und C. Paar, „Electromagnetic enclosure PUF for tamper proofing commodity hardware and other applications“, 2020.
    [18]
    S. Ghandali, T. Moos, A. Moradi, und C. Paar, „Side-channel hardware trojan for provably-secure SCA-protected implementations“, 2020.
    [1]
    S. Wallat u. a., „Highway to HAL: open-sourcing the first extendable gate-level netlist reverse engineering framework“, in ACM International Conference on Computing Frontiers 2019 (CF 2019), proceedings, Alghero, 2019, S. 392–397. doi: 10.1145/3310273.3323419.
    [2]
    C. Wiesen u. a., „Towards cognitive obfuscation: impeding hardware reverse engineering based on psychological insights“, in ASP-DAC 2019, Tokyo, 2019, S. 104–111. doi: 10.1145/3287624.3288741.
    [3]
    M. Fyrbiak u. a., „HAL – the missing piece of the puzzle for hardware reverse engineering, trojan detection and insertion“, IEEE transactions on dependable and secure computing / Institute of Electrical and Electronics Engineers, Bd. 16, Nr. 3, S. 498–510, 2019, doi: 10.1109/tdsc.2018.2812183.
    [4]
    M. Ender, P. Swierczynski, S. Wallat, M. Wilhelm, P. M. Knopp, und C. Paar, „Insights into the mind of a trojan designer: the challenge to integrate a trojan into the bitstream“, in ASP-DAC 2019, Tokyo, 2019, S. 112–119. doi: 10.1145/3287624.3288742.
    [5]
    T. Oder, T. Güneysu, P. Schwabe, und C. Paar, „Efficient and side-channel resistant implementation of lattice-based cryptography“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2019. doi: 10.13154/294-6902.
    [6]
    M. Fyrbiak, S. Wallat, S. Reinhard, N. Bissantz, und C. Paar, „Graph similarity and its applications to hardware security“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 69, Nr. 4, S. 505–519, Nov. 2019, doi: 10.1109/tc.2019.2953752.
    [7]
    S. Becker, C. Wiesen, C. Paar, und N. Rummel, „Wie arbeiten Reverse Engineers?: Interdisziplinäre Forschung zum Verständnis technischer und kognitiver Prozesse beim Hardware-Reverse-Engineering“, Datenschutz und Datensicherheit, Bd. 43, Nr. 11, S. 686–690, Nov. 2019, doi: 10.1007/s11623-019-1190-7.
    [8]
    C. Wiesen, S. Becker, N. Albartus, C. Paar, und N. Rummel, „Promoting the acquisition of hardware reverse engineering skills“, in 2019 IEEE Frontiers in Education Conference (FIE 2019), Cincinnati, Ohio , 2019, S. 566–574. doi: 10.1109/fie43999.2019.9028668.
    [9]
    M. Fyrbiak, S. Wallat, S. Reinhard, N. Bissantz, und C. Paar, „Graph similarity and its applications to hardware security“, 2019.
    [10]
    C. Wiesen, S. Becker, N. Albartus, C. Paar, und N. Rummel, „Promoting the acquisition of hardware reverse engineering skills“, 2019.
    [11]
    A. Wichmann, M. A. Sasse, und C. Paar, „IT-Sicherheit ist mehr als Technik “, Datenschutz und Datensicherheit, Bd. 43, S. 673–674, 2019, doi: 10.1007/s11623-019-1186-3.
    [1]
    B. Kollenda, P. Koppe, M. Fyrbiak, C. Kison, C. Paar, und T. Holz, „An exploratory analysis of microcode as a building block for system defenses“, in CCS’18, Toronto, Ont., 2018, S. 1649–1666. doi: 10.1145/3243734.3243861.
    [2]
    P. Swierczynski, G. T. Becker, A. Moradi, und C. Paar, „Bitstream Fault Injections (BiFI) – automated fault attacks against SRAM-based FPGAs“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 67, Nr. 3, S. 348–360, 2018, doi: 10.1109/tc.2016.2646367.
    [3]
    C. Wiesen u. a., „Teaching hardware reverse engineering: educational guidelines and practical insights“, in 2018 IEEE International Conference on Teaching, Assessment, and Learning for Engineering (TALE 2018), Wollongong, 2018, S. 438–445. doi: 10.1109/tale.2018.8615270.
    [4]
    M. Fyrbiak, S. Rokicki, N. Bissantz, R. Tessier, und C. Paar, „Hybrid obfuscation to protect against disclosure attacks on embedded microprocessors“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 67, Nr. 3, S. 307–321, 2018, doi: 10.1109/tc.2017.2649520.
    [5]
    M. Hoffmann und C. Paar, „Stealthy opaque predicates in hardware – obfuscating constant expressions at negligible overhead“, IACR transactions on cryptographic hardware and embedded systems, Bd. 2018, Nr. 2, S. 277–297, Mai 2018, doi: 10.13154/tches.v2018.i2.277-297.
    [6]
    C. S. F. Huth, T. Güneysu, A. Sezgin, und C. Paar, „Physical-layer security architectures for the internet of things“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2018.
    [7]
    K. Jansen, A. Sezgin, C. Pöpper, C. Paar, und I. Martinovic, „Detection and localization of attacks on satellite-based navigation systems“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2018. doi: 10.13154/294-6388.
    [8]
    M. Fyrbiak u. a., „On the difficulty of FSM-based hardware obfuscation“, IACR transactions on cryptographic hardware and embedded systems, Bd. 2018, Nr. 3, S. 293–330, Aug. 2018, doi: 10.13154/tches.v2018.i3.293-330.
    [9]
    S. Keshavarz, F. Schellenberg, B. Richter, C. Paar, und D. Holcomb, „SAT-based reverse engineering of gate-level schematics using fault injection and probing“, in 2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2018), Washington, DC, 2018, S. 215–220. doi: 10.1109/hst.2018.8383918.
    [10]
    M. Fyrbiak, C. Paar, R. Tessier, und T. Güneysu, „Constructive and destructive reverse engineering aspects of digital systems“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2018. doi: 10.13154/294-6473.
    [11]
    F. Schellenberg, C. Paar, D. Holcomb, und T. Güneysu, „Novel methods of passive and active side-channel attacks“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2018. doi: 10.13154/294-6020.
    [12]
    C. Kison, C. Paar, J.-P. Seifert, und T. Güneysu, „Advanced methods for hardware reverse engineering“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2018. doi: 10.13154/294-6537.
    [13]
    B. Kollenda, P. Koppe, M. Fyrbiak, C. Kison, C. Paar, und T. Holz, „An exploratory analysis of microcode as a building block for system defenses“, 2018.
    [14]
    P. Swierczynski, G. T. Becker, A. Moradi, und C. Paar, „Bitstream Fault Injections (BiFI) – automated fault attacks against SRAM-based FPGAs“, 2018.
    [15]
    S. Keshavarz, F. Schellenberg, B. Richter, C. Paar, und D. Holcomb, „SAT-based reverse engineering of gate-level schematics using fault injection and probing“, 24. Februar 2018.
    [1]
    C. Paar, „Hardware trojans and other threats against embedded systems“, in ASIA CCS ’17, Abu Dhabi, 2017, S. 1. doi: 10.1145/3052973.3053885.
    [2]
    M. Ender, S. Ghandali, A. Moradi, und C. Paar, „The first thorough side-channel hardware Trojan“, in Advances in cryptology – ASIACRYPT 2017, Hongkong, 2017, Bd. 10624–10626, S. 755–780. doi: 10.1007/978-3-319-70694-8_26.
    [3]
    P. Koppe u. a., „Reverse engineering x86 processor microcode“, in Proceedings of the 26th USENIX Security Symposium, Vancouver (British Columbia), 2017, S. 1163–1180.
    [4]
    A. Vijayakumar, V. C. Patil, D. E. Holcomb, C. Paar, und S. Kundu, „Physical design obfuscation of hardware: a comprehensive investigation of device and logic-level techniques“, IEEE transactions on information forensics and security / Institute of Electrical and Electronics Engineers, Bd. 12, Nr. 1, S. 64–77, 2017, doi: 10.1109/tifs.2016.2601067.
    [5]
    C. Zenger, C. Paar, H. Boche, und T. Güneysu, „Physical-layer security for the internet of things“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2017.
    [6]
    S. Wallat, M. Fyrbiak, M. Schlögel, und C. Paar, „A look at the dark side of hardware reverse engineering – a case study“, in 2017 2nd International Verification and Security Workshop (IVSW 2017), Thessaloniki, 2017, S. 95–100. doi: 10.1109/ivsw.2017.8031551.
    [7]
    C. Zenger u. a., „Implementing a real-time capable WPLS testbed for independent performance and security analyses“, in 2017 51st Asilomar Conference on Signals, Systems, and Computers (ACSSC 2017), Pacific Grove, Calif, 2017, S. 9–13. doi: 10.1109/acssc.2017.8335125.
    [8]
    P. Wehner, D. Göhringer, C. Paar, M. Hübner, und H. Blume, „Simulation von Mehrkernsystemen mit Network-on-Chip Kommunikation“, Verlag Dr. Hut, München, 2017.
    [9]
    S. Keshavarz, C. Paar, und D. Holcomb, „Design automation for obfuscated circuits with multiple viable functions“, in 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE 2017), Lausanne, 2017, S. 886–889. doi: 10.23919/date.2017.7927112.
    [10]
    P. Swierczynski, C. Paar, R. Tessier, und T. Güneysu, „Bitstream-based attacks against reconfigurable hardware“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2017.
    [11]
    M. Fyrbiak u. a., „Hardware reverse engineering: overview and open challenges“, in 2017 2nd International Verification and Security Workshop (IVSW 2017), Thessaloniki, 2017, S. 88–94. doi: 10.1109/ivsw.2017.8031550.
    [12]
    C. Zenger, M. Pietersz, und C. Paar, „Relay-Verhinderung und Schlüssel-Diversifizierung mittels Wireless Physical-Layer Security“, gehalten auf der Innosecure, Düsseldorf, 31. Mai 2017, Publiziert.
    [13]
    S. Wallat, M. Fyrbiak, M. Schlögel, und C. Paar, „A look at the dark side of hardware reverse engineering – a case study“, 2017.
    [14]
    M. Fyrbiak u. a., „Hardware reverse engineering: overview and open challenges“, 2017.
    [15]
    M. Ender, S. Ghandali, A. Moradi, und C. Paar, „The first thorough side-channel hardware Trojan“, 2017.
    [1]
    F. Schellenberg, M. Finkeldey, N. C. Gerhardt, M. R. Hofmann, A. Moradi, und C. Paar, „Large laser spots and fault sensitivity analysis“, in 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2016), McLean, Va., 2016, S. 203–208. doi: 10.1109/hst.2016.7495583.
    [2]
    P. Samarin, K. Lemke-Rust, und C. Paar, „IP core protection using voltage-controlled side-channel receivers“, in 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST 2016), McLean, Va., 2016, S. 217–222. doi: 10.1109/hst.2016.7495585.
    [3]
    P. Swierczynski, M. Fyrbiak, P. Koppe, A. Moradi, und C. Paar, „Interdiction in practice – hardware Trojan against a high-security USB flash drive“, Journal of cryptographic engineering, Bd. 7, Nr. 3, S. 199–211, Juni 2016, doi: 10.1007/s13389-016-0132-7.
    [4]
    M. Finkeldey, F. Schellenberg, N. C. Gerhardt, C. Paar, und M. R. Hofmann, „Common-path depth-filtered digital holography for high resolution imaging of buried semiconductor structures“, in Practical Holography XXX: Materials and Applications, San Francisco, Calif., 2016, Bd. 9771. doi: 10.1117/12.2212454.
    [5]
    F. Schellenberg u. a., „On the complexity reduction of laser fault injection campaigns using OBIC measurements“, in 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography – FDTC 2015, Saint Malo, März 2016, S. 14–27. doi: 10.1109/fdtc.2015.10.
    [6]
    C. Zenger, H. Vogt, J. Zimmer, A. Sezgin, und C. Paar, „The passive eavesdropper affects my channel: secret-key rates under real-world conditions“, in 2016 IEEE Globecom Workshops (GC Wkshps 2016), Washington, DC, 2016, S. 641–646. doi: 10.1109/glocomw.2016.7849064.
    [7]
    A. Wild, T. Güneysu, A. Moradi, und C. Paar, „Structure-aware design of security primitives on reconfigurable hardware“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2016.
    [8]
    N. Aviram u. a., „DROWN: Breaking TLS using SSLv2“, in Proceedings of the 25th USENIX Security Symposium, Austin, Tex., 2016, S. 689–706. [Online]. Verfügbar unter: https://www.usenix.org/sites/default/files/sec16-full_proceedings.pdf
    [9]
    C. Zenger, M. Pietersz, J. Zimmer, J.-F. Posielek, T. Lenze, und C. Paar, „Authenticated key establishment for low-resource devices exploiting correlated random channels“, Computer networks, Bd. 109, Nr. Part 1, S. 105–123, Nov. 2016, doi: 10.1016/j.comnet.2016.06.013.
    [10]
    S. Ghandali, G. T. Becker, D. Holcomb, und C. Paar, „A design methodology for stealthy parametric trojans and its application to bug attacks“, in Cryptographic Hardware and Embedded Systems, Santa Barbara, Calif., 2016, Bd. 9813, S. 625–647. doi: 10.1007/978-3-662-53140-2_30.
    [11]
    C. Zenger, M. Pietersz, und C. Paar, „Preventing relay attacks and providing perfect forward secrecy using PHYSEC on 8-bit µC“, in 2016 IEEE International Conference on Communications Workshops (ICC) took place May 23-28, 2016 in Kuala Lumpur, Malaysia, Kuala Lumpur, 2016, S. 110–115. doi: 10.1109/iccw.2016.7503773.
    [12]
    C. Zenger, J. Zimmer, M. Pietersz, B. Driessen, und C. Paar, „Constructive and destructive aspects of adaptive wormholes for the 5G tactile internet“, in WiSec ’16, Darmstadt, 2016, S. 109–120. doi: 10.1145/2939918.2939923.
    [13]
    I. von Maurich, T. Güneysu, und C. Paar, „Efficient implementation of code- and hash-based cryptography“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2016.
    [14]
    T. Bartkewitz, C. Paar, K. Lemke-Rust, und J. Schwenk, „Towards efficient practical side-channel cryptanalysis: improved implementations, novel methods, applications, and real-world attacks“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2016. [Online]. Verfügbar unter: https://hss-opus.ub.ruhr-uni-bochum.de/opus4/frontdoor/index/index/docId/5393
    [15]
    D. J. Bernstein u. a., „Faster discrete logarithms on FPGAs“, 2016. http://eprint.iacr.org/2016/382
    [16]
    S. Ghandali, G. T. Becker, D. Holcomb, und C. Paar, „A design methodology for stealthy parametric trojans and its application to bug attacks“, 2016.
    [17]
    C. Zenger, M. Pietersz, J. Zimmer, J.-F. Posielek, T. Lenze, und C. Paar, „Authenticated key establishment for low-resource devices exploiting correlated random channels“, 2016.
    [18]
    C. Zenger, J. Zimmer, M. Pietersz, B. Driessen, und C. Paar, „Constructive and destructive aspects of adaptive wormholes for the 5G tactile internet“, 2016.
    [19]
    F. Schellenberg, M. Finkeldey, N. C. Gerhardt, M. R. Hofmann, A. Moradi, und C. Paar, „Large laser spots and fault sensitivity analysis“, 2016.
    [20]
    C. Zenger, M. Pietersz, und C. Paar, „Preventing relay attacks and providing perfect forward secrecy using PHYSEC on 8-bit µC“, 2016. [Online]. Verfügbar unter: https://informatik.rub.de/veroeffentlichungen/emsec/2016/pdfs/2016_Preventing_Relay_Attacks_and_Providing_Perfect_Forward_Secrecy_using_PHYSEC_on_8_bit_%C2%B5C.pdf
    [21]
    C. Zenger, H. Vogt, J. Zimmer, A. Sezgin, und C. Paar, „The passive eavesdropper affects my channel: secret-key rates under real-world conditions“, 2016.
    [22]
    A. Moradi, C. Paar, und S. Mangard, „Advances in side-channel security“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2016. [Online]. Verfügbar unter: https://hss-opus.ub.ruhr-uni-bochum.de/opus4/frontdoor/deliver/index/docId/4574/file/diss.pdf
    [1]
    C. Zenger, J. Zimmer, J.-F. Posielek, und C. Paar, „On-line entropy estimation for secure information reconciliation“, Juli 2015.
    [2]
    C. Zenger, J. Zimmer, und C. Paar, „Security analysis of quantization schemes for channel-based key extraction“, gehalten auf der Workshop on Wireless Communication Security at the Physical Layer, Coimbra, 22. Juli 2015, Publiziert.
    [3]
    A.-T. Donda, P. Samarin, J. Samotyja, K. Lemke-Rust, und C. Paar, „Remote IP protection using timing channels“, in Information security and cryptology – ICISC 2014, 2015, Bd. 8949, S. 222–237. doi: 10.1007/978-3-319-15943-0_14.
    [4]
    S. Malik, G. T. Becker, C. Paar, und W. P. Burleson, „Development of a layout-level hardware obfuscation tool“, in IEEE Computer society annual symposium on VLSI (ISVLSI 2015), 2015, S. 204–209. doi: 10.1109/isvlsi.2015.118.
    [5]
    M. Hassan, A. Khalid, A. Chattopadhyay, C. Rechberger, T. Güneysu, und C. Paar, „New ASIC/FPGA cost estimates for SHA-1 collisions“, in 2015 Euromicro Conference on Digital System Design (DSD 2015), 2015, S. 669–676. doi: 10.1109/dsd.2015.78.
    [6]
    P. Swierczynski, M. Fyrbiak, C. Paar, C. Huriaux, und R. Tessier, „Protecting against cryptographic trojans in FPGAs“, in 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2015), Vancouver, British Columbia, 2015, S. 151–154. doi: 10.1109/fccm.2015.55.
    [7]
    L. A. Benthin Sanguino, N.-G. Leander, C. Paar, B. Esslinger, und I. Niebel, „Analyzing the Spanish strip cipher by combining combinatorial and statistical methods“, Cryptologia, 2015, Publiziert, doi: 10.1080/01611194.2015.1050332.
    [8]
    A. Gornik, A. Moradi, J. Oehm, und C. Paar, „A hardware-based countermeasure to reduce side-channel leakage: design, implementation, and evaluation“, IEEE transactions on computer-aided design of integrated circuits and systems / Institute of Electrical and Electronics Engineers, Bd. 34, Nr. 8, S. 1308–1319, 2015, doi: 10.1109/tcad.2015.2423274.
    [9]
    A. Rupp, F. Baldimtsi, G. Hinterwälder, und C. Paar, „Cryptographic theory meets practice: efficient and privacy-preserving payments for public transport“, ACM transactions on information and system security, Bd. 17, Nr. 3, Art. Nr. 10, 2015, doi: 10.1145/2699904.
    [10]
    P. Swierczynski, A. Moradi, D. Oswald, und C. Paar, „Physical security evaluation of the bitstream encryption mechanism of Altera Stratix II and Stratix III FPGAs“, ACM transactions on reconfigurable technology and systems, Bd. 7, Nr. 4, Art. Nr. 34, 2015, doi: 10.1145/2629462.
    [11]
    C. Zenger, A. Ambekar, F. Winzer, T. Pöppelmann, H. D. Schotten, und C. Paar, „Preventing scaling of successful attacks: a cross-layer security architecture for resource-constrained platforms“, in Cryptography and information security in the Balkans, Istanbul, 2015, Bd. 9024, S. 103–120. doi: 10.1007/978-3-319-21356-9_8.
    [12]
    D. Strobel, F. Bache, D. Oswald, F. Schellenberg, und C. Paar, „SCANDALee: a Side-ChANnel-based DisAssembLer using local electromagnetic emanations“, in 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE 2015), Grenoble, 2015, S. 139–144. doi: 10.7873/date.2015.0639.
    [13]
    P. Swierczynski, M. Fyrbiak, P. Koppe, und C. Paar, „FPGA trojans through detecting and weakening of cryptographic primitives“, IEEE transactions on computer-aided design of integrated circuits and systems / Institute of Electrical and Electronics Engineers, Bd. 34, Nr. 8, S. 1236–1249, 2015, doi: 10.1109/tcad.2015.2399455.
    [14]
    C. Zenger, J. Zimmer, M. Pietersz, J.-F. Posielek, und C. Paar, „Exploiting the physical environment for securing the internet of things“, in Proceedings of the 2015 New Security Paradigms Workshop (NSPW 2015), Twente, 2015, S. 44–58. doi: 10.1145/2841113.2841117.
    [15]
    M. Düll u. a., „High-speed Curve25519 on 8-bit, 16-bit, and 32-bit microcontrollers“, Designs, codes and cryptography, Bd. 77, Nr. 2–3, S. 493–514, 2015, doi: 10.1007/s10623-015-0087-1.
    [16]
    R. Guillaume, F. Winzer, A. Czylwik, C. Zenger, und C. Paar, „Bringing PHY-based key generation into the field: an evaluation for practical scenarios“, in 2015 IEEE 82nd Vehicular Technology Conference (VTC Fall), Boston, Mass., 2015, Publiziert. doi: 10.1109/vtcfall.2015.7390857.
    [17]
    C. Zenger, J. Zimmer, und C. Paar, „Security analysis of quantization schemes for channel-based key extraction“, EAI endorsed transactions on security and safety / European Alliance for Innovation, Bd. 2, Nr. 6, 2015, doi: 10.4108/eai.22-7-2015.2260194.
    [18]
    G. Hinterwälder, A. Moradi, M. Hutter, P. Schwabe, und C. Paar, „Full-size high-security ECC implementation on MSP430 microcontrollers“, in Progress in cryptology – LATINCRYPT 2014, Florianópolis, 2015, Bd. 8895, S. 31–47. doi: 10.1007/978-3-319-16295-9_2.
    [19]
    C. Kison, J. Frinken, und C. Paar, „Finding the AES bits in the haystack: reverse engineering and SCA using voltage contrast“, in Cryptographic hardware and embedded systems – CHES 2015, Saint-Malo, 2015, Bd. 9293, S. 641–660. doi: 10.1007/978-3-662-48324-4_32.
    [20]
    G. Hinterwälder, F. Riek, und C. Paar, „Efficient e-cash with attributes on MULTOS smartcards“, in Radio frequency identification, New York, NY, 2015, Bd. 9440, S. 141–155. doi: 10.1007/978-3-319-24837-0_9.
    [21]
    A. Gornik, A. Moradi, J. Oehm, und C. Paar, „A hardware-based countermeasure to reduce side-channel leakage: design, implementation, and evaluation“, 2015.
    [22]
    R. Guillaume, F. Winzer, A. Czylwik, C. Zenger, und C. Paar, „Bringing PHY-based key generation into the field: an evaluation for practical scenarios“, 2015.
    [23]
    S. Malik, G. T. Becker, C. Paar, und W. P. Burleson, „Development of a layout-level hardware obfuscation tool“, 2015.
    [24]
    G. Hinterwälder, F. Riek, und C. Paar, „Efficient e-cash with attributes on MULTOS smartcards“, 2015.
    [25]
    P. Swierczynski, M. Fyrbiak, P. Koppe, und C. Paar, „FPGA trojans through detecting and weakening of cryptographic primitives“, 2015.
    [26]
    F. Schellenberg u. a., „On the complexity reduction of laser fault injection campaigns using OBIC measurements“, 2015.
    [27]
    P. Swierczynski, M. Fyrbiak, C. Paar, C. Huriaux, und R. Tessier, „Protecting against cryptographic trojans in FPGAs“, 2015.
    [28]
    D. Strobel, F. Bache, D. Oswald, F. Schellenberg, und C. Paar, „SCANDALee: a Side-ChANnel-based DisAssembLer using local electromagnetic emanations“, 2015.
    [29]
    C. Zenger, J. Zimmer, und C. Paar, „Security analysis of quantization schemes for channel-based key extraction“, 2015.
    [1]
    D. Strobel und C. Paar, „Novel applications for side-channel analyses of embedded microcontrollers“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2014. [Online]. Verfügbar unter: http://www-brs.ub.ruhr-uni-bochum.de/netahtml/HSS/Diss/StrobelDaehyun/diss.pdf
    [2]
    C. Zenger, J. Förster, und C. Paar, „Implementation and evaluation of channel-based key establishment systems“, Sep. 2014.
    [3]
    D. V. Bailey, M. Dürmuth, und C. Paar, „‚Typing‘ passwords with voice recognition: or: how to authenticate to Google Glass“, gehalten auf der Adventures in Authentication: WAY Workshop, Menlo Park, 9. Juli 2014, Publiziert.
    [4]
    S. Wetzel, B. Borsch, C. Paar, und T. Pöppelmann, „Proof-of-concept: using homomorphic cryptography to provide for privacy in modern vehicular environments“, gehalten auf der escar, Detroit, 21. Juni 2014, Publiziert.
    [5]
    C. Paar, „How to build hardware trojans“, in Proceedings of the 4th International Workshop on Trustworthy Embedded Devices (TrustED 2014), 2014, S. 57. doi: 10.1145/2666141.2668384.
    [6]
    G. T. Becker, F. Regazzoni, C. Paar, und W. P. Burleson, „Stealthy dopant-level hardware Trojans: extended version“, Journal of cryptographic engineering, Bd. 4, Nr. 1, S. 19–31, 2014, doi: 10.1007/s13389-013-0068-0.
    [7]
    M. R. Albrecht, B. Driessen, E. B. Kavun, N.-G. Leander, C. Paar, und T. Yalcin, „Block ciphers – focus on the linear layer (feat. PRIDE)“, in Advances in cryptology – CRYPTO 2014, Santa Barbara, Calif., 2014, Bd. 8616/8617, S. 57–76. doi: 10.1007/978-3-662-44371-2_4.
    [8]
    M. R. Albrecht, B. Driessen, E. B. Kavun, N.-G. Leander, C. Paar, und T. Yalcin, „Block ciphers – focus on the linear layer (feat. PRIDE): full version“, 15. Juni 2014. http://eprint.iacr.org/2014/453
    [9]
    D. Strobel, D. Oswald, B. Richter, F. Schellenberg, und C. Paar, „Microcontrollers as (in)security devices for pervasive computing applications“, Proceedings of the IEEE / Institute of Electrical and Electronics Engineers, Bd. 102, Nr. 8, S. 1157–1173, 2014, doi: 10.1109/jproc.2014.2325397.
    [10]
    C. Zenger, M.-J. Chur, J.-F. Posielek, C. Paar, und G. Wunder, „A novel key generating architecture for wireless low-resource devices“, in 2014 International Workshop on Secure Internet of Things (SIoT 2014), Breslau, 2014, S. 26–34. doi: 10.1109/siot.2014.7.
    [11]
    T. Kasper, D. Oswald, und C. Paar, „Sweet dreams and nightmares: security in the internet of things“, in Information security theory and practice, Heraklion, 2014, Bd. 8501, S. 1–9. doi: 10.1007/978-3-662-43826-8_1.
    [12]
    S. Heyse, R. Zimmermann, und C. Paar, „Attacking code-based cryptosystems with information set decoding using special-purpose hardware“, in Post-quantum cryptography, Waterloo, Ontario, 2014, Bd. 8772, S. 126–141. doi: 10.1007/978-3-319-11659-4_8.
    [13]
    R. Guillaume, A. Mueller, C. Zenger, C. Paar, und A. Czylwik, „Fair comparison and evaluation of quantization schemes for PHY-based key generation“, Proceedings of the 18th International OFDM Workshop 2014 (InOWo’14). VDE-Verlag, Berlin [u.a.], S. 150–154, 2014. [Online]. Verfügbar unter: http://ieeexplore.ieee.org/document/6924270/
    [14]
    D. V. Bailey, M. Dürmuth, und C. Paar, „Statistics on password re-use and adaptive strength for financial accounts“, in Security and cryptography for networks, 2014, Bd. 8642, S. 218–235. doi: 10.1007/978-3-319-10879-7_13.
    [15]
    C. Zenger, M.-J. Chur, J.-F. Posielek, C. Paar, und G. Wunder, „A novel key generating architecture for wireless low-resource devices“, 2014.
    [16]
    S. Heyse, R. Zimmermann, und C. Paar, „Attacking code-based cryptosystems with information set decoding using special-purpose hardware“, 2014.
    [17]
    G. Hinterwälder, A. Moradi, M. Hutter, P. Schwabe, und C. Paar, „Full-size high-security ECC implementation on MSP430 microcontrollers“, 2014.
    [18]
    P. Swierczynski, A. Moradi, D. Oswald, und C. Paar, „Physical security evaluation of the bitstream encryption mechanism of Altera Stratix II and Stratix III FPGAs“, 2014.
    [19]
    C. Zenger, A. Ambekar, F. Winzer, T. Pöppelmann, H. D. Schotten, und C. Paar, „Preventing scaling of successful attacks: a cross-layer security architecture for resource-constrained platforms“, 2014.
    [20]
    A.-T. Donda, P. Samarin, J. Samotyja, K. Lemke-Rust, und C. Paar, „Remote IP protection using timing channels“, 2014.
    [21]
    D. V. Bailey, M. Dürmuth, und C. Paar, „Statistics on password re-use and adaptive strength for financial accounts“, 2014.
    [22]
    G. T. Becker, F. Regazzoni, C. Paar, und W. P. Burleson, „Stealthy dopant-level hardware Trojans: extended version“, 2014.
    [23]
    T. Kasper, D. Oswald, und C. Paar, „Sweet dreams and nightmares: security in the internet of things“, 2014.
    [24]
    D. V. Bailey, M. Dürmuth, und C. Paar, „‚Typing‘ passwords with voice recognition: or: how to authenticate to Google Glass“, 2014.
    [1]
    S. Heyse und C. Paar, „Post quantum cryptography: Implementing alternative public key schemes of embedded devices ; preparing for the rise of quantum computers“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2013. [Online]. Verfügbar unter: http://www-brs.ub.ruhr-uni-bochum.de/netahtml/HSS/Diss/HeyseStefan/diss.pdf
    [2]
    D. Oswald, D. Strobel, F. Schellenberg, T. Kasper, und C. Paar, „When reverse-engineering meets side-channel analysis: digital lockpicking in practice“, in Selected areas in cryptography – SAC 2013, Burnaby, BC, Aug. 2013, Bd. 8282, S. 571–588. doi: 10.1007/978-3-662-43414-7_29.
    [3]
    D. Oswald und C. Paar, „Implementation attacks: From theory to practice“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2013. [Online]. Verfügbar unter: http://www-brs.ub.ruhr-uni-bochum.de/netahtml/HSS/Diss/OswaldDavid/diss.pdf
    [4]
    D. Oswald, B. Richter, und C. Paar, „Side-channel attacks on the Yubikey 2 one-time password generator“, in Research in attacks, intrusions and defenses, Rodney Bay, St. Lucia, 2013, Bd. 8145, S. 204–222. doi: 10.1007/978-3-642-41284-4_11.
    [5]
    D. Oswald und C. Paar, „Improving side-channel analysis with optimal linear transforms“, in Smart card research and advanced applications, Graz, 2013, Bd. 7771, S. 219–233. doi: 10.1007/978-3-642-37288-9_15.
    [6]
    T. Güneysu, T. Kasper, M. Novotný, C. Paar, L. Wienbrandt, und R. Zimmermann, „High-Performance cryptanalysis on RIVYERA and COPACOBANA computing systems“, in High-performance computing using FPGAs, W. Vanderbauwhede und K. Benkrid, Hrsg. New York, NY [u.a.]: Springer, 2013, S. 335–366. doi: 10.1007/978-1-4614-1791-0_11.
    [7]
    D. Strobel u. a., „Fuming acid and cryptanalysis: handy tools for overcoming a digital locking and access control system“, in Advances in cryptology – CRYPTO 2013, Santa Barbara, Calif., 2013, Bd. 8042–8043, S. 147–164. doi: 10.1007/978-3-642-40041-4_9.
    [8]
    G. Hinterwälder, C. Zenger, F. Baldimtsi, A. Lysyanskaya, C. Paar, und W. P. Burleson, „Efficient E-Cash in practice: NFC-based payments for public transportation systems“, in Privacy enhancing technologies, Bloomington, IN, 2013, Bd. 7981, S. 40–59. doi: 10.1007/978-3-642-39077-7_3.
    [9]
    S. Engels, E. B. Kavun, C. Paar, T. Yalcin, und H. Mihajloska, „A non-linear/linear instruction set extension for lightweight ciphers“, in 2013 21st IEEE Symposium on Computer Arithmetic (ARITH), 2013, S. 67–75. doi: 10.1109/arith.2013.36.
    [10]
    A. Moradi, D. Oswald, C. Paar, und P. Swierczynski, „Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering“, in Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, Calif., 2013, S. 91–100. doi: 10.1145/2435264.2435282.
    [11]
    B. Driessen, R. Hund, C. Willems, C. Paar, und T. Holz, „An experimental security analysis of two satphone standards“, ACM transactions on information and system security, Bd. 16, Nr. 3, S. 1–30, 2013, doi: 10.1145/2535522.
    [12]
    A. Rupp, G. Hinterwälder, F. Baldimtsi, und C. Paar, „P4R: Privacy-preserving pre-payments with refunds for transportation systems“, in Financial cryptography and data security, Okinawa, 2013, Bd. 7859, S. 205–212. doi: 10.1007/978-3-642-39884-1_17.
    [13]
    T. Eisenbarth, I. von Maurich, C. Paar, und X. Ye, „A performance boost for hash-based signatures“, in Number theory and cryptography, Bd. 8260, M. Fischlin und S. Katzenbeisser, Hrsg. Berlin [u.a.]: Springer, 2013, S. 166–182. doi: 10.1007/978-3-642-42001-6_13.
    [14]
    P. Swierczynski, N.-G. Leander, und C. Paar, „Keccak und der SHA-2“, Datenschutz und Datensicherheit, Bd. 37, Nr. 11, S. 712–719, 2013, doi: 10.1007/s11623-013-0299-3.
    [15]
    G. T. Becker, F. Regazzoni, C. Paar, und W. P. Burleson, „Stealthy dopant-level hardware trojans“, in Cryptographic hardware and embedded systems – CHES 2013, Santa Barbara, Calif., 2013, Bd. 8086, S. 197–214. doi: 10.1007/978-3-642-40349-1_12.
    [16]
    C. Paar, „‚NSA is watching you‘: IT-Sicherheitsexperte der RUB beleuchtet den Abhörskandal“, Rubin Sonderheft, Nr. 2, S. 47–49, 2013, [Online]. Verfügbar unter: http://rubin.rub.de/sites/default/files/rubin/2013-herbst/09-nsa/09_beitrag_nsa_rubin_2013_2.pdf
    [17]
    G. Hinterwälder, C. Paar, und W. P. Burleson, „Privacy preserving payments on computational RFID devices with application in intelligent transportation systems“, in Radio frequency identification, Nijmegen, 2013, Bd. 7739, S. 109–122. doi: 10.1007/978-3-642-36140-1_8.
    [18]
    P. Swierczynski und C. Paar, „SHA-3-Portierung auf einer ATmega163 Smartcard“, in 23. SIT-SmartCard-Workshop, Darmstadt, 2013, S. 116–127.
    [19]
    T. Kasper, A. Kühn, D. Oswald, C. Zenger, und C. Paar, „Rights management with NFC smartphones and electronic ID cards: a proof of concept for modern car sharing“, in Radio frequency identification, Graz, 2013, Bd. 8262, S. 34–53. doi: 10.1007/978-3-642-41332-2_3.
    [20]
    B. Driessen, C. Paar, und R. Anderson, „Practical cryptanalysis of real-world systems: an engineer’s approach“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2013.
    [21]
    L. Batina u. a., „Dietary recommendations for lightweight block ciphers: power, energy and area analysis of recently developed architectures“, in Radio frequency identification, Graz, 2013, Bd. 8262, S. 103–112. doi: 10.1007/978-3-642-41332-2_7.
    [22]
    T. Eisenbarth, I. von Maurich, C. Paar, und X. Ye, „A performance boost for hash-based signatures“, 2013.
    [23]
    G. Hinterwälder, C. Zenger, F. Baldimtsi, A. Lysyanskaya, C. Paar, und W. P. Burleson, „Efficient E-Cash in practice: NFC-based payments for public transportation systems“, 2013.
    [24]
    M. Dürmuth, T. Güneysu, M. Kasper, C. Paar, T. Yalcin, und R. Zimmermann, „Evaluation of standardized password-based key derivation against parallel processing platforms“, 2013.
    [25]
    A. Moradi, O. M. Mischke, und C. Paar, „One attack to rule them all: collision timing attack versus 42 AES ASIC cores“, 2013.
    [26]
    A. Rupp, G. Hinterwälder, F. Baldimtsi, und C. Paar, „P4R: pPrivacy-preserving pre-payments with refunds for transportation systems“, 2013.
    [27]
    T. Kasper, A. Kühn, D. Oswald, C. Zenger, und C. Paar, „Rights management with NFC smartphones and electronic ID cards: a proof of concept for modern car sharing“, 2013.
    [28]
    A. Moradi, D. Oswald, C. Paar, und P. Swierczynski, „Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering“, 2013.
    [29]
    D. Oswald, B. Richter, und C. Paar, „Side-channel attacks on the Yubikey 2 one-time password generator“, 2013.
    [30]
    G. T. Becker, F. Regazzoni, C. Paar, und Wayne P. Burleson, „Stealthy dopant-level hardware trojans“, 2013.
    [1]
    B. Driessen und C. Paar, „Solving binary linear equation systems over the rationals and binaries“, Juli 2012.
    [2]
    B. Driessen und C. Paar, „Solving binary linear equation systems over the rationals and binaries“, in Arithmetic of finite fields, Bochum, Juli 2012, Bd. 7369, S. 187–195. doi: 10.1007/978-3-642-31662-3_13.
    [3]
    I. Dinur, T. Güneysu, C. Paar, A. Shamir, und R. Zimmermann, „Experimentally verifying a complex algebraic attack on the grain-128 cipher using dedicated reconfigurable hardware“, in SHARCS 2012, Washington D.C., März 2012, S. 155–168.
    [4]
    G. T. Becker, D. Strobel, C. Paar, und W. Burleson, „Detecting software theft in embedded systems: a side-channel approach“, IEEE transactions on information forensics and security / Institute of Electrical and Electronics Engineers, Bd. 7, Nr. 4, S. 1144–1154, 2012, doi: 10.1109/tifs.2012.2191964.
    [5]
    A. Moradi, M. Kasper, und C. Paar, „Black-box side-channel attacks highlight the importance of countermeasures: an analysis of the xilinx virtex-4 and virtex-5 bitstream encryption mechanism“, in Topics in cryptology – CT-RSA 2012, 2012, Bd. 7178, S. 1–18. doi: 10.1007/978-3-642-27954-6_1.
    [6]
    B. Driessen, R. Hund, C. Willems, C. Paar, und T. Holz, „Don’t trust satellite phones: a security analysis of two satphone standards“, in 2012 IEEE Symposium on Security and Privacy (SP 2012), Piscataway, NJ, 2012, S. 128–142. doi: 10.1109/sp.2012.18.
    [7]
    M. Dürmuth, T. Güneysu, M. Kasper, C. Paar, T. Yalcin, und R. Zimmermann, „Evaluation of standardized password-based key derivation against parallel processing platforms“, in Computer security – ESORICS 2012, Pisa, 2012, Bd. 7459, S. 716–733. doi: 10.1007/978-3-642-33167-1_41.
    [8]
    M. Kasper u. a., „Side channels as building blocks“, Journal of cryptographic engineering, Bd. 2, Nr. 3, S. 143–159, 2012, doi: 10.1007/s13389-012-0040-4.
    [9]
    C. Paar, „The yin and yang sides of embedded security: (extended abstract)“, in Trusted systems, 2012, Bd. 7711, S. 112–115. doi: 10.1007/978-3-642-35371-0_10.
    [10]
    A. Moradi, M. Kirschbaum, T. Eisenbarth, und C. Paar, „Masked dual-rail precharge logic encounters state-of-the-art power analysis methods“, IEEE transactions on very large scale integration (VLSI) systems / Institute of Electrical and Electronics Engineers, Bd. 20, Nr. 9, S. 1578–1589, 2012, doi: 10.1109/tvlsi.2011.2160375.
    [11]
    B. Driessen, T. Güneysu, E. B. Kavun, O. M. Mischke, C. Paar, und T. Pöppelmann, „IPSecco: a lightweight and reconfigurable IPSec core“, in 2012 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2012), 2012, S. 316–322. doi: 10.1109/reconfig.2012.6416757.
    [12]
    D. Strobel und C. Paar, „An efficient method for eliminating random delays in power traces of embedded software“, in Information security and cryptology – ICISC 2011, Seoul, 2012, Bd. 7259, S. 48–60. doi: 10.1007/978-3-642-31912-9_4.
    [13]
    T. Kasper, D. Oswald, und C. Paar, „Side-channel analysis of cryptographic RFIDs with analog demodulation“, in RFID security and privacy, 2012, Bd. 7055, S. 61–77. doi: 10.1007/978-3-642-25286-0_5.
    [14]
    A. Moradi, O. M. Mischke, und C. Paar, „One attack to rule them all: collision timing attack versus 42 AES ASIC cores“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 62, Nr. 9, S. 1786–1798, 2012, doi: 10.1109/tc.2012.154.
    [15]
    J. Borghoff u. a., „PRINCE: a low-latency block cipher for pervasive computing applications ; full version“, 2012. https://eprint.iacr.org/2012/529
    [16]
    J. Borghoff u. a., „PRINCE: a low-latency block cipher for pervasive computing applications“, in Advances in Cryptology – ASIACRYPT 2012, Beijing, China, 2012, Bd. 7658, S. 208–225. doi: 10.1007/978-3-642-34961-4_14.
    [17]
    S. Heyse, E. Kiltz, V. Lyubashevsky, C. Paar, und K. Pietrzak, „Lapin: an efficient authentication protocol based on Ring-LPN“, in Fast software encryption, 2012, Bd. 7549, S. 346–365. doi: 10.1007/978-3-642-34047-5_20.
    [18]
    F. Baldimtsi, G. Hinterwälder, A. Rupp, A. Lysyanskaya, C. Paar, und W. P. Burleson, „Pay as you go“, 5th workshop on Hot topics in Privacy Enhancing Technologies (HotPETs 2012). S. 109–117, 2012.
    [19]
    A. Juels, D. Oswald, und C. Paar, Hrsg., RFID security and privacy: 7th international workshop RFIDSec 2011, Amherst, MA, USA, June 26 – 28, 2011 ; revised selected papers. Berlin [u.a.]: Springer, 2012. doi: 10.1007/978-3-642-25286-0.
    [20]
    T. Kasper, D. Oswald, und C. Paar, „Security of wireless embedded devices in the real world“, in ISSE 2011, Prag, 2012, 1. ed., S. 174–189. doi: 10.1007/978-3-8348-8652-1_16.
    [21]
    C. Paar, M. Wolf, und I. von Maurich, „IT-Sicherheit in der Elektromobilität“, ATZ-Elektronik, Bd. 7, Nr. 4, S. 274–279, 2012, doi: 10.1365/s35658-012-0174-2.
    [22]
    D. Oswald und C. Paar, „Improving side-channel analysis with optimal linear transforms“, 2012.
    [23]
    G. T. Becker, D. Strobel, C. Paar, und W. P. Burleson, „Detecting software theft in embedded systems: a side-channel approach“, 2012.
    [24]
    I. Dinur, T. Güneysu, C. Paar, A. Shamir, und R. Zimmermann, „Experimentally verifying a complex algebraic attack on the grain-128 cipher using dedicated reconfigurable hardware“, 2012.
    [25]
    B. Driessen, T. Güneysu, E. B. Kavun, O. M. Mischke, C. Paar, und T. Pöppelmann, „IPSecco: a lightweight and reconfigurable IPSec core“, 2012.
    [26]
    M. Kasper u. a., „Side channels as building blocks“, 2012.
    [1]
    D. Oswald und C. Paar, „Breaking mifare DESfire MF3ICD40: power analysis and templates in the real world“, 2011.
    [2]
    Y. Chen u. a., „On the vulnerability of FPGA bitstream encryption against power analysis attacks“, Okt. 2011. [Online]. Verfügbar unter: http://emsec.rub.de/media/crypto/veroeffentlichungen/2011/11/28/V2pro-CCS.pdf
    [3]
    T. Kasper und C. Paar, „Security analysis of pervasive wireless devices: Physical and protocol attacks in practice“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2011. [Online]. Verfügbar unter: http://www-brs.ub.ruhr-uni-bochum.de/netahtml/HSS/Diss/KasperTimo/diss.pdf
    [4]
    I. Dinur, T. Güneysu, C. Paar, A. Shamir, und R. Zimmermann, „An experimentally verified attack on full grain-128 using dedicated reconfigurable hardware“, in Advances in cryptology – ASIACRYPT 2011, Seoul, 2011, Bd. 7073, S. 327–343. doi: 10.1007/978-3-642-25385-0_18.
    [5]
    G. T. Becker, W. Burleson, und C. Paar, „Side-channel watermarks for embedded software“, in 2011 9th IEEE International NEWCAS Conference, 2011, S. 478–481. doi: 10.1109/newcas.2011.5981323.
    [6]
    A. Moradi, A. Barenghi, T. Kasper, und C. Paar, „On the vul­nerabi­li­ty of FPGA bit­stream en­cryp­ti­on against power ana­ly­sis at­tacks: extrac­ting keys from Xi­l­inx Vir­tex-II FPGAs“, in Proceedings of the 18th ACM Conference on Computer and Communications Security, Chicago, Ill., 2011, S. 111–124. doi: 10.1145/2046707.2046722.
    [7]
    D. V. Bailey, J. Brainard, S. Rohde, und C. Paar, „Wireless authentication and transaction-confirmation token“, in E-Business and telecommunications, 2011, Bd. 130, S. 186–198. doi: 10.1007/978-3-642-20077-9_13.
    [8]
    T. Kasper, I. von Maurich, D. Oswald, und C. Paar, „Chameleon: a versatile emulator for contactless smartcards“, in Information Security and Cryptology – ICISC 2010, Seoul, 2011, 1. Aufl., Bd. 6829, S. 189–206. doi: 10.1007/978-3-642-24209-0_13.
    [9]
    A. Moradi, A. Y. Poschmann, S. Ling, C. Paar, und H. Wang, „Pushing the limits: a very compact and a threshold implementation of AES“, in Advances in cryptology – EUROCRYPT 2011, Tallinn, Estland, 2011, Bd. 6632, S. 69–88. doi: 10.1007/978-3-642-20465-4_6.
    [10]
    A. Moradi, O. M. Mischke, und C. Paar, „Practical evaluation of DPA countermeasures on reconfigurable hardware“, in 2011 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST 2011), San Diego, Calif., 2011, S. 154–160. doi: 10.1109/hst.2011.5955014.
    [11]
    C. Paar, J.-J. Quisquater, und B. Sunar, „Guest Editorial“, in Journal of cryptology, Bd. 24, Nr. 2, New York, NY: Springer, 2011, S. 245–246. doi: 10.1007/s00145-011-9099-9.
    [12]
    T. Güneysu, S. Heyse, und C. Paar, „The future of high-speed cryptography: new computing platforms and new ciphers“, in Proceedings of the 2011 Great Lakes Symposium on VLSI, Lausanne, 2011, S. 461–466. doi: 10.1145/1973009.1973112.
    [13]
    A. Moradi, O. M. Mischke, C. Paar, Y. Li, K. Ohta, und K. Sakiyama, „On the power of fault sen­si­ti­vi­ty ana­ly­sis and col­li­si­on si­de-chan­nel at­tacks in a com­bined set­ting“, in Cryptographic hardware and embedded systems – CHES 2011, Nara, 2011, Bd. 6917, S. 292–311. doi: 10.1007/978-3-642-23951-9_20.
    [14]
    T. Kasper, D. Oswald, und C. Paar, „Wireless security threats: eavesdropping and detecting of active RFIDs and remote controls in the wild“, in 2011 19th international conference on software, telecommunications and computer networks, Dubrovnik, 2011, Publiziert. [Online]. Verfügbar unter: http://ieeexplore.ieee.org/document/6064450/
    [15]
    A. Moradi, M. Kasper, und C. Paar, „On the portability of side-channel attacks: an analysis of the Xilinx Virtex 4 and Virtex 5 bitstream encryption mechanism“, 2011. [Online]. Verfügbar unter: http://eprint.iacr.org/2011/391
    [16]
    M. Kasper, T. Kasper, A. Moradi, und C. Paar, „Praktische Angriffe auf die Bitstromverschlüsselung von Xilinx FPGAs“, Datenschutz und Datensicherheit, Bd. 35, Nr. 11, S. 779–785, 2011, doi: 10.1007/s11623-011-0185-9.
    [17]
    T. Kasper, D. Oswald, und C. Paar, „Seitenkanalanalyse kontaktloser SmartCards“, Datenschutz und Datensicherheit, Bd. 35, Nr. 11, S. 786–790, 2011, doi: 10.1007/s11623-011-0186-8.
    [18]
    D. Oswald und C. Paar, „Breaking mifare DESfire MF3ICD40: power analysis and templates in the real world“, in Cryptographic hardware and embedded systems – CHES 2011, Nara, 2011, Bd. 6917, S. 207–222. doi: 10.1007/978-3-642-23951-9_14.
    [19]
    C. Paar, „The yin and yang sides of embedded security“, Progress in cryptology – INDOCRYPT 2011, Bd. 7107. Springer, Berlin [u.a.], S. 93, 2011. doi: 10.1007/978-3-642-25578-6_8.
    [20]
    I. Dinur, T. Güneysu, C. Paar, A. Shamir, und R. Zimmermann, „An experimentally verified attack on full grain-128 using dedicated reconfigurable hardware“, 2011.
    [21]
    A. Moradi, M. Kirschbaum, T. Eisenbarth, und C. Paar, „Masked dual-rail precharge logic encounters state-of-the-art power analysis methods“, 2011.
    [22]
    A. Moradi, O. M. Mischke, C. Paar, Y. Li, K. Ohta, und K. Sakiyama, „On the power of fault sen­si­ti­vi­ty ana­ly­sis and col­li­si­on si­de-chan­nel at­tacks in a com­bined set­ting“, 2011.
    [23]
    A. Moradi, O. M. Mischke, und C. Paar, „Practical evaluation of DPA countermeasures on reconfigurable hardware“, 2011.
    [24]
    A. Moradi, A. Y. Poschmann, S. Ling, C. Paar, und H. Wang, „Pushing the limits: a very compact and a threshold implementation of AES“, 2011.
    [25]
    T. Kasper, D. Oswald, und C. Paar, „Side-channel analysis of cryptographic RFIDs with analog demodulation“, 2011.
    [26]
    G. T. Becker, W. Burleson, und C. Paar, „Side-channel watermarks for embedded software“, 2011.
    [1]
    T. Kasper, I. von Maurich, D. Oswald, und C. Paar, „Cloning cryptographic RFID cards for 25$“, gehalten auf der Benelux Workshop on Information and System Security, Nimwegen, 29. November 2010, Publiziert.
    [2]
    S. Heyse u. a., „Evaluation of SHA-3 candidates for 8-bit embedded processors“, gehalten auf der SHA-e Candidate Conference, Santa Barbara, Calif., 24. August 2010, Publiziert.
    [3]
    T. Kasper, M. Silbermann, und C. Paar, „All you can eat or breaking a real-world contactless payment system: (short paper)“, in Financial cryptography and data security, Teneriffa, Spanien, 2010, Bd. 6054, S. 343–350. doi: 10.1007/978-3-642-14577-3_28.
    [4]
    T. Eisenbarth, C. Paar, und B. Weghenkel, „Building a side channel based disassembler“, in Transactions on computational science X, Bd. 6340, M. L. Gavrilova, C. J. K. Tan, und E. D. Moreno, Hrsg. Berlin [u.a.]: Springer, 2010, S. 78–99. doi: 10.1007/978-3-642-17499-5_4.
    [5]
    A. Y. Poschmann, M. J. B. Robshaw, F. Vater, und C. Paar, „Lightweight cryptography and RFID: tackling the hidden overhead“, KSII Transactions on Internet and Information Systems, Bd. 4, Nr. 2, S. 98–116, 2010, doi: 10.3837/tiis.2010.04.002.
    [6]
    A. Moradi, T. Eisenbarth, A. Y. Poschmann, und C. Paar, „Power analysis of single-rail storage elements as used in MDPL“, in Information security and cryptology – ICISC 2009, Seoul, Korea, 2010, Bd. 5984, S. 146–160. doi: 10.1007/978-3-642-14423-3_11.
    [7]
    T. Kasper, D. Oswald, und C. Paar, „A versatile framework for implementation attacks on cryptographic RFIDs and embedded devices“, in Transactions on computational science X, Bd. 6340, M. L. Gavrilova, C. J. K. Tan, und E. D. Moreno, Hrsg. Berlin [u.a.]: Springer, 2010, S. 100–130. doi: 10.1007/978-3-642-17499-5_5.
    [8]
    J. Fan, D. V. Bailey, L. Batina, T. Güneysu, C. Paar, und I. M. R. Verbauwhede, „Breaking elliptic curve cryptosystems using reconfigurable hardware“, in 2010 International Conference on Field Programmable Logic and Applications (FPL 2010), Mailand, 2010, S. 133–138. doi: 10.1109/fpl.2010.34.
    [9]
    S. Heyse, A. Moradi, und C. Paar, „Practical power analysis attacks on software implementations of McEliece“, in Post-quantum cryptography, Darmstadt, 2010, Bd. 6061, S. 108–125. doi: 10.1007/978-3-642-12929-2_9.
    [10]
    A. Bogdanov, T. Eisenbarth, C. Paar, und M. Wienecke, „Differential cache-collision timing attacks on AES with applications to embedded CPUs“, in Topics in cryptology – CT-RSA 2010, 2010, Bd. 5985, S. 235–251. doi: 10.1007/978-3-642-11925-5_17.
    [11]
    A. Y. Poschmann, M. J. B. Robshaw, F. Vater, und C. Paar, „Lightweight cryptography and RFID: tackling the hidden overheads“, in Information security and cryptology – ICISC 2009, Seoul, Korea, 2010, Bd. 5984, S. 129–145. doi: 10.1007/978-3-642-14423-3_10.
    [12]
    R. Zimmermann, T. Güneysu, und C. Paar, „High-performance integer factoring with reconfigurable devices“, in 2010 International Conference on Field Programmable Logic and Applications (FPL 2010), Mailand, 2010, S. 83–88. doi: 10.1109/fpl.2010.26.
    [13]
    G. T. Becker, M. Kasper, A. Moradi, und C. Paar, „Side-channel based watermarks for integrated circuits“, in Proceedings of the 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Anaheim, Calif., 2010, S. 30–35. doi: 10.1109/hst.2010.5513117.
    [14]
    G. T. Becker, S. C. Lo, D. S. De Lorenzo, P. K. Enge, und C. Paar, „Secure location verification: a security analysis of GPS signal authentication“, in Data and applications security and privacy XXIV, Rom, 2010, Bd. 6166, S. 366–373. doi: 10.1007/978-3-642-13739-6_29.
    [15]
    S. Drimer, T. Güneysu, und C. Paar, „DSPs, BRAMs, and a pinch of logic: extended recipes for AES on FPGAs“, ACM transactions on reconfigurable technology and systems, Bd. 3, Nr. 1, Art. Nr. 3, 2010, doi: 10.1145/1661438.1661441.
    [16]
    T. Güneysu und C. Paar, „Transforming write collisions in block RAMs into security applications“, in 2009 International conference on field-programmable technology, N. Bergmann, Hrsg. Piscataway, NJ: IEEE, 2010, S. 128–134. doi: 10.1109/fpt.2009.5377631.
    [17]
    C. Paar, J. Pelzl, und T. Wollinger, „Efficient security solutions for embedded applications“, in Proceedings & conference materials, 2010, Publiziert.
    [18]
    C. Paar und J. Pelzl, Understanding cryptography: a textbook for students and practitioners. Berlin: Springer, 2010. doi: 10.1007/978-3-642-04101-3.
    [19]
    J. Fan, D. V. Bailey, L. Batina, T. Güneysu, C. Paar, und I. M. R. Verbauwhede, „Breaking elliptic curves cryptosystems using reconfigurable hardware“, in Proceedings of the ECRYPT Workshop on Tools for Cryptanalysis 2010, 2010, S. 71–84. [Online]. Verfügbar unter: http://www.ecrypt.eu.org/symlab/tools2010/tools2010-proceedings.pdf
    [20]
    S. Heyse u. a., „Evaluation of SHA-3 candidates for 8-bit embedded processors“, 2010. [Online]. Verfügbar unter: http://csrc.nist.gov/groups/ST/hash/sha-3/Round2/Aug2010/documents/papers/HEYSE_EvaluationSHA-3Candidatesfor8-bitProcessors.pdf
    [21]
    G. T. Becker, M. Kasper, A. Moradi, und C. Paar, „Si­de-chan­nel based wa­ter­marks for IP pro­tec­tion“, in COSADE 2010, Darmstadt, 2010, S. 47–50. [Online]. Verfügbar unter: http://cosade2010.cased.de/files/proceedings/cosade2010_paper_9.pdf
    [22]
    T. Güneysu und C. Paar, „Modular integer arithmetic for public key cryptography“, in Secure integrated circuits and systems, 1. Aufl., I. M. R. Verbauwhede, Hrsg. New York [u.a.]: Springer, 2010, S. 3–26. doi: 10.1007/978-0-387-71829-3_1.
    [23]
    K. Schmeh und C. Paar, Die Welt der geheimen Zeichen: die faszinierende Geschichte der Verschlüsselung. Hamburg: Nikol, 2010.
    [24]
    T. Kasper, I. von Maurich, D. Oswald, und C. Paar, „Cloning Cryptographic RFID Cards for 25$“, 2010. [Online]. Verfügbar unter: http://ambition4.org/download/148
    [25]
    T. Kasper, D. Oswald, und C. Paar, „A versatile framework for implementation attacks on cryptographic RFIDs and embedded devices“, 2010.
    [26]
    T. Kasper, M. Silbermann, und C. Paar, „All you can eat or breaking a real-world contactless payment system“, 2010.
    [27]
    T. Kasper, I. von Maurich, D. Oswald, und C. Paar, „Chameleon: a versatile emulator for contactless smartcards“, 2010.
    [28]
    A. Bogdanov, T. Eisenbarth, C. Paar, und M. Wienecke, „Differential cache-collision timing attacks on AES with applications to embedded CPUs“, 2010.
    [29]
    S. Heyse, A. Moradi, und C. Paar, „Practical power analysis attacks on software implementations of McEliece“, 2010.
    [30]
    G. T. Becker, Sherman C. Lo, D. S. De Lorenzo, Per K. Enge, und C. Paar, „Secure location verification: a security analysis of GPS signal authentication“, 2010.
    [1]
    D. V. Bailey u. a., „The certicom challenges ECC2-X“, gehalten auf der SHARCS’09 – Special-purpose Hardware for Attacking Cryptographic Systems, Lausanne, 9. September 2009, Publiziert. [Online]. Verfügbar unter: http://cr.yp.to/talks/2009.09.09/slides.pdf
    [2]
    T. Kasper, D. Oswald, und C. Paar, „New methods for cost-effective side-channel attacks on cryptographic RFIDs“, 30. Juni 2009, Publiziert.
    [3]
    M. Vogt, A. Y. Poschmann, und C. Paar, „Cryptography is feasible on 4-bit microcontrollers – a proof of concept“, in 2009 IEEE international conference on RFID (IEEE RFID) : Orlando, Florida, USA, 27 – 28 April 2009, 2009, S. 233–240. doi: 10.1109/rfid.2009.4911182.
    [4]
    M. Sbeiti, M. Silbermann, A. Y. Poschmann, und C. Paar, „Design space exploration of present implementations for FPGAS“, in 2009 5th Southern Conference on Programmable Logic, 2009, S. 141–145. doi: 10.1109/spl.2009.4914893.
    [5]
    T. Kasper, D. Oswald, und C. Paar, „EM side-channel attacks on commercial contactless smartcards using low-cost equipment“, in Information security applications, 2009, Bd. 5932, S. 79–93. doi: 10.1007/978-3-642-10838-9_7.
    [6]
    A. Moradi, N. Mousavi, C. Paar, und M. Salmasizadeh, „A comparative study of mutual information analysis under a Gaussian assumption“, in Information security applications, 2009, Bd. 5932, S. 193–205. doi: 10.1007/978-3-642-10838-9_15.
    [7]
    C. Paar, „Crypto Engineering: some history and some case studies“, in Cryptographic hardware and embedded systems – CHES 2009, Lausanne, 2009, Bd. 5747, S. 220–224. doi: 10.1007/978-3-642-04138-9_16.
    [8]
    A. Y. Poschmann, C. Paar, und M. J. B. Robshaw, „Lightweight cryptography: cryptographic engineering for a pervasive world“, Europ. Univ. Verlag, Berlin, 2009.
    [9]
    C. Paar, T. Eisenbarth, M. Kasper, T. Kasper, und A. Moradi, „KeeLoq and side-channel analysis: evolution of an attack“, in Workshop on fault diagnosis and tolerance in cryptography (FDTC), 2009, 2009, S. 65–69. doi: 10.1109/fdtc.2009.44.
    [10]
    F. Regazzoni u. a., „Evaluating resistance of MCML technology to power analysis attacks using a simulation-based methodology“, in Transactions on computational science IV, 2009, Bd. 5430, S. 230–243. doi: 10.1007/978-3-642-01004-0_13.
    [11]
    T. Eisenbarth, T. Güneysu, S. Heyse, und C. Paar, „MicroEliece: McEliece for embedded devices“, in Cryptographic hardware and embedded systems – CHES 2009, Lausanne, 2009, Bd. 5747, S. 49–64. doi: 10.1007/978-3-642-04138-9_4.
    [12]
    L. Lin, M. Kasper, T. Güneysu, C. Paar, und W. Burleson, „Trojan side-channels: lightweight hardware trojans through side-channel engineering“, in Cryptographic hardware and embedded systems – CHES 2009, Lausanne, 2009, Bd. 5747, S. 382–395. doi: 10.1007/978-3-642-04138-9_27.
    [13]
    J. Guajardo Merchan, T. Güneysu, S. S. Kumar, und C. Paar, „Secure IP-block distribution for hardware devices“, in 2009 IEEE international workshop on hardware-oriented security and trust, 2009, S. 82–89. doi: 10.1109/hst.2009.5224965.
    [14]
    A. Y. Poschmann, N.-G. Leander, K. Schramm, und C. Paar, „A family of light-weight block ciphers based on DES suited for RFID applications“, 2009.
    [15]
    G. T. Becker, S. C. Lo, D. S. de Lorenzo, D. Qiu, C. Paar, und P. K. Enge, „Efficient authentication mechanisms for navigation systems – a radio-navigation case study“, in Proceedings fo the 22nd international technical meeting of the Satellite Division of the Institute of Navigation, ION GNSS 2009 : Sept. 22 – 25, 2009, Savanna Convention Center, Savannah, Georgia, 2009, S. 901–912.
    [16]
    L. Lin, W. P. Burleson, und C. Paar, „MOLES: malicious off-chip leakage enabled by side-channels“, in 2009 IEEE/ACM International Conference on Computer-Aided Design digest of technical papers, 2009, S. 117–122. [Online]. Verfügbar unter: http://ieeexplore.ieee.org/xpls/icp.jsp?arnumber=5361303
    [17]
    M. Kasper, T. Kasper, A. Moradi, und C. Paar, „Breaking KEELOQ in a flash: on extracting keys at lightning speed“, in Progress in cryptology – Africacrypt <2, 2009, Gammarth>, Bd. 5580, B. Preneel, Hrsg. Berlin: Springer, 2009, S. 403–420. doi: 10.1007/978-3-642-02384-2_25.
    [18]
    D. V. Bailey, J. Brainard, S. Rohde, und C. Paar, „One-touch financial transaction authentication“, in Proceedings of the international conference on security and cryptography, 2009, S. 5–12. doi: 10.5220/0002182400050012.
    [19]
    J. Guajardo Merchan, T. Güneysu, S. S. Kumar, und C. Paar, 2009 IEEE international workshop on hardware-oriented security and trust: HOST ’09 ; San Francisco, California, USA, 27 July 2009. Piscataway, NJ: IEEE, 2009.
    [20]
    T. Güneysu, G. Pfeiffer, C. Paar, und M. Schimmler, „Three years of evolution: cryptanalysis with Copacobana“, 2009.
    [21]
    C. Paar, J. Pelzl, A. Rupp, K. Schramm, und A. Weimerskirch, „Elektroautos und IT security: Sicherheit für alternative Transportsysteme“, 2009. [Online]. Verfügbar unter: https://informatik.rub.de/veroeffentlichungen/emsec/2009/pdfs/2009_Green_Car_Security__IT_Sicherheit_und_Elektromobilit%C3%A4t.pdf
    [22]
    C. Paar, A. Rupp, K. Schramm, A. Weimerskirch, und W. Burleson, „Securing green cars: IT security in next-generation electric vehicle systems“, 2009.
    [23]
    T. Kasper, D. Oswald, und C. Paar, „New methods for cost-effective side-channel attacks on cryptographic RFIDs“, 2009. [Online]. Verfügbar unter: http://www.cosic.esat.kuleuven.be/rfidsec09/Papers/31_datenfeuer_rfidsec.pdf
    [24]
    A. Moradi, N. Mousavi, C. Paar, und M. Salmasizadeh, „A comparative study of mutual information analysis under a Gaussian assumption“, 2009.
    [25]
    M. Kasper, T. Kasper, A. Moradi, und C. Paar, „Breaking KEELOQ in a flash: on extracting keys at lightning speed“, 2009.
    [26]
    C. Paar, „Crypto engineering: some history and some case studies“, 2009.
    [27]
    M. Vogt, A. Y. Poschmann, und C. Paar, „Cryptography is feasible on 4-bit microcontrollers – a proof of concept“, 2009.
    [28]
    M. Sbeiti, M. Silbermann, A. Y. Poschmann, und C. Paar, „Design space exploration of present implementations for FPGAS“, 2009.
    [29]
    T. Kasper, D. Oswald, und C. Paar, „EM side-channel attacks on commercial contactless smartcards using low-cost equipment“, 2009.
    [30]
    F. Regazzoni u. a., „Evaluating resistance of MCML technology to power analysis attacks using a simulation-based methodology“, 2009.
    [31]
    C. Paar, T. Eisenbarth, M. Kasper, T. Kasper, und A. Moradi, „KeeLoq and side-channel analysis: evolution of an attack“, 2009.
    [32]
    T. Eisenbarth, T. Güneysu, S. Heyse, und C. Paar, „MicroEliece: McEliece for embedded devices“, 2009.
    [33]
    D. V. Bailey, J. Brainard, S. Rohde, und C. Paar, „One-touch financial transaction authentication“, 2009.
    [34]
    A. Moradi, T. Eisenbarth, A. Y. Poschmann, und C. Paar, „Power analysis of single-rail storage elements as used in MDPL“, 2009.
    [35]
    J. Guajardo Merchan, T. Güneysu, S. S. Kumar, und C. Paar, „Secure IP-block distribution for hardware devices“, 2009.
    [36]
    L. Lin, M. Kasper, T. Güneysu, C. Paar, und W. Burleson, „Trojan side-channels: lightweight hardware trojans through side-channel engineering“, Poster-Abstract, 2009.
    [1]
    C. Paar, „The next 10 years of IT security: RFID, BMWs and burglars: invited talk at Stanford University“, 20. August 2008, Publiziert. [Online]. Verfügbar unter: http://imperia.rz.rub.de:9085/imperia/md/content/texte/publications/selectedtalks/stanford2008_embedded_security.pdf
    [2]
    S. Balasubramanian, A. Bogdanov, A. Rupp, J. Ding, H. W. Carter, und C. Paar, „Fast multivariate signature generation in hardware: the case of rainbow“, 2. Juli 2008, Publiziert.
    [3]
    G. Meiser, T. Eisenbarth, K. Lemke-Rust, und C. Paar, „Efficient implementation of eSTREAM ciphers on 8-bit AVR microcontrollers“, in 2008 International Symposium on Industrial Embedded Systems, La Grande Motte, 2008, S. 58–66. doi: 10.1109/sies.2008.4577681.
    [4]
    T. Güneysu und C. Paar, „Ultra high performance ECC over NIST primes on commercial FPGAs“, in Cryptographic hardware and embedded systems – CHES 2008, Washington, DC, 2008, Bd. 5154, S. 62–78. doi: 10.1007/978-3-540-85053-3_5.
    [5]
    T. Güneysu, T. Kasper, M. Novotný, C. Paar, und A. Rupp, „Cryptanalysis with COPACOBANA“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 57, Nr. 11, S. 1498–1513, 2008, doi: 10.1109/tc.2008.80.
    [6]
    T. Güneysu, C. Paar, und J. Pelzl, „Special-purpose hardware for solving the elliptic curve discrete logarithm problem“, ACM transactions on reconfigurable technology and systems, Bd. 1, Nr. 2, 2008, doi: 10.1145/1371579.1371580.
    [7]
    T. Eisenbarth, T. Kasper, A. Moradi, C. Paar, M. Salmasizadeh, und M. T. Shalmani, „On the power of power analysis in the real world: a complete break of the KEELOQ code hopping scheme“, in Advances in Cryptology – CRYPTO 2008, Santa Barbara, Calif., 2008, Bd. 5157, S. 203–220. doi: 10.1007/978-3-540-85174-5_12.
    [8]
    B. Driessen, A. Y. Poschmann, und C. Paar, „Comparison of innovative signature algorithms for WSNs“, in WiSec’08, Alexandria, VA, 2008, S. 30–35. doi: 10.1145/1352533.1352539.
    [9]
    S. Rohde, T. Eisenbarth, E. Dahmen, J. Buchmann, und C. Paar, „Fast hash-based signatures on constrained devices“, in Smart card research and advanced applications, London, 2008, Bd. 5189, S. 104–117. doi: 10.1007/978-3-540-85893-5_8.
    [10]
    C. Rolfes, A. Y. Poschmann, N.-G. Leander, und C. Paar, „Ultra-lightweight implementations for smart devices – security for 1000 gate equivalents“, in Smart card research and advanced applications, London, 2008, Bd. 5189, S. 89–103. doi: 10.1007/978-3-540-85893-5_7.
    [11]
    S. Drimer, T. Güneysu, und C. Paar, „DSPs, BRAMs and a pinch of logic: new recipes for AES on FPGAs“, in Proceedings of the Sixteenth IEEE Symposium on Field-Programmable Custom Computing Machines, Palo Alto, Calif., 2008, S. 99–108. doi: 10.1109/fccm.2008.42.
    [12]
    A. Bogdanov, N.-G. Leander, C. Paar, A. Y. Poschmann, M. J. B. Robshaw, und Y. Seurin, „Hash functions and RFID tags: mind the gap“, in Cryptographic hardware and embedded systems – CHES 2008, Washington, DC, 2008, Bd. 5154, S. 283–299. doi: 10.1007/978-3-540-85053-3_18.
    [13]
    C. Rolfes, A. Y. Poschmann, N.-G. Leander, und C. Paar, „Security for 1000 gate equivalents“, 2008.
    [14]
    T. Güneysu, C. Paar, G. Pfeiffer, und M. Schimmler, „Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis“, in 2008 International Conference on Field Programmable Logic and Applications, Heidelberg, 2008, S. 675–677. doi: 10.1109/fpl.2008.4630037.
    [15]
    T. Güneysu, C. Paar, und S. Schäge, „Efficient hash collision search strategies on special-purpose hardware“, in Research in cryptology, Bochum, 2008, Bd. 4945, S. 39–51. doi: 10.1007/978-3-540-88353-1_4.
    [16]
    T. Eisenbarth, T. Kasper, und C. Paar, „Sicherheit moderner Funktüröffnersysteme“, Datenschutz und Datensicherheit, Bd. 32, Nr. 8, S. 507–510, Okt. 2008, doi: 10.1007/s11623-008-0121-9.
    [17]
    M. Wolf und C. Paar, „Security requirements engineering in the automotive domain: on specification procedures and implementational aspects“, in Sicherheit 2008, Saarbrücken, 2008, Bd. 128, S. 485–498. [Online]. Verfügbar unter: https://dl.gi.de/handle/20.500.12116/21500
    [18]
    T. Güneysu und C. Paar, „Breaking legacy banking standards with special-purpose hardware“, in Financial cryptography and data security, Cozumel, 2008, Bd. 5143, S. 128–140. doi: 10.1007/978-3-540-85230-8_10.
    [19]
    S. Drimer, T. Güneysu, M. G. Kuhn, und C. Paar, „Protecting multiple cores in a single FPGA design“, 2008. [Online]. Verfügbar unter: http://www.cl.cam.ac.uk/~sd410/papers/protect_many_cores.pdf
    [20]
    T. Güneysu und C. Paar, „Breaking legacy banking standards with special-purpose hardware“, 2008.
    [21]
    S. Rohde, T. Eisenbarth, E. Dahmen, J. Buchmann, und C. Paar, „Fast hash-based signatures on constrained devices“, 2008.
    [22]
    J. Pelzl, M. Šimka, T. Kleinjung, M. Drutarovský, V. Fischer, und C. Paar, „Area-time efficient hardware architecture for factoring integers with the elliptic curve method“, 19. Juni 2008. https://hal.science/ujm-00289036v1
    [1]
    T. Eisenbarth, T. Güneysu, C. Paar, A.-R. Sadeghi, R. Tessier, und M. Wolf, „Trusted computing in reconfigurable hardware“, 3. Juli 2007, Publiziert.
    [2]
    T. Eisenbarth, T. Güneysu, C. Paar, A.-R. Sadeghi, M. Wolf, und R. Tessier, „Establishing chain of trust in reconfigurable hardware“, in 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2007, 2007, S. 289–290. doi: 10.1109/fccm.2007.23.
    [3]
    T. Eisenbarth, T. Güneysu, C. Paar, A.-R. Sadeghi, D. Schellekens, und M. Wolf, „Reconfigurable trusted computing in hardware“, in STC ’07, 2007, S. 15–20. doi: 10.1145/1314354.1314360.
    [4]
    F. Regazzoni u. a., „A simulation-based methodology for evaluating the DPA-Resistance of cryptographic functional units with application to CMOS and MCML technologies“, in International conference on embedded computer systems, 2007, S. 209–214. doi: 10.1109/icsamos.2007.4285753.
    [5]
    T. Güneysu, B. Möller, und C. Paar, „New protection mechanisms for intellectual property in recononfigurable logic“, in 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2007, 2007, S. 287–288. doi: 10.1109/fccm.2007.22.
    [6]
    A. Y. Poschmann, N.-G. Leander, K. Schramm, und C. Paar, „New light-weight crypto algorithms for RFID“, in 2007 IEEE International Symposium on Circuits and Systems, 2007, S. 1843–1846. doi: 10.1109/iscas.2007.378273.
    [7]
    T. Eisenbarth, C. Paar, A. Y. Poschmann, S. S. Kumar, und L. Uhsadel, „A survey of lightweight-cryptography implementations“, IEEE design & test of computers / Institute of Electrical and Electronics Engineers, Bd. 24, Nr. 6, S. 522–533, 2007, doi: 10.1109/mdt.2007.178.
    [8]
    T. Güneysu, B. Möller, und C. Paar, „Dynamic intellectual property protection for reconfigurable devices“, in 2007 International Conference on Field-Programmable Technology, 2007, S. 169–176. doi: 10.1109/fpt.2007.4439246.
    [9]
    C. Paar und A. Weimerskirch, „Embedded security in a pervasive world“, Information security technical report, Bd. 12, Nr. 3, S. 155–161, 2007, doi: 10.1016/j.istr.2007.05.006.
    [10]
    F. Regazzoni u. a., „Power attacks resistance of cryptographic S-boxes with added error detection circuits“, in Proceedings / The 22nd IEEE international symposium on defect and fault-tolerance in VLSI systems, DFT 2007 : 26 – 28 September 2007, Rome, Italy, 2007, S. 508–516. doi: 10.1109/dft.2007.61.
    [11]
    T. Güneysu, C. Paar, und J. Pelzl, „Attacking elliptic curve cryptosystems with special-purpose hardware“, in FPGA 2007, Fifteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2007, S. 207–215. doi: 10.1145/1216919.1216953.
    [12]
    A. Bogdanov u. a., „Present: an ultra-lightweight block cipher“, in Cryptographic hardware and embedded systems – CHES 2007, Wien, 2007, Bd. 4727, S. 450–466. doi: 10.1007/978-3-540-74735-2_31.
    [13]
    N.-G. Leander, C. Paar, A. Y. Poschmann, und K. Schramm, „New lightweight DES variants“, in Fast software encryption, 2007, Bd. 4593, S. 196–210. doi: 10.1007/978-3-540-74619-5_13.
    [14]
    A. Bogdanov u. a., „Small-footprint block cipher design: how far can you go?“, 2007. [Online]. Verfügbar unter: http://www.rfidsec07.etsit.uma.es/slides/papers/paper-44.pdf
    [15]
    A. Bogdanov u. a., „Small-footprint block cipher design: how far can you go?“, 2007. [Online]. Verfügbar unter: http://www.rfidsec07.etsit.uma.es/slides/present/slides-4.4.PDF
    [16]
    T. Güneysu, C. Paar, J. Pelzl, G. Pfeiffer, M. Schimmler, und C. Schleiffer, „Parallel computing with low-cost FPGAs: a framework for COPACOBANA“, in Parallel computing, 2007, Bd. 15, S. 741–748.
    [17]
    S. Baktır, S. S. Kumar, C. Paar, und B. Sunar, „A state-of-the-art elliptic curve cryptographic processor operating in the frequency domain“, Mobile networks and applications, Bd. 12, Nr. 4, S. 259–270, 2007, doi: 10.1007/s11036-007-0022-4.
    [18]
    C. Paar und A. Y. Poschmann, „Hardware optimierte leichtgewichtige Blockchiffren für RFID- und Sensor-Systeme“, in Informatik 2007: Informatik trifft Logistik, Bremen, 2007, Bd. 109 / 110, S. 200–204. [Online]. Verfügbar unter: http://subs.emis.de/LNI/Proceedings/Proceedings110/gi-proc-110-036.pdf
    [19]
    L. Uhsadel, A. Y. Poschmann, und C. Paar, „An efficient general purpose elliptic curve cryptography module for ubiquitous sensor networks“, 2007.
    [20]
    S. Rinne, T. Eisenbarth, und C. Paar, „Performance analysis of contemporary light-weight block ciphers on 8-bit microcontrollers“, 2007. [Online]. Verfügbar unter: http://www.soerenrinne.de/data/lw_speed2007.pdf
    [21]
    T. Gendrullis, T. Kasper, und C. Paar, „A lightweight hardware implementation of the stream cipher VEST-4“, 2007.
    [22]
    D. Carluccio, K. Lemke-Rust, C. Paar, und A.-R. Sadeghi, „E-passport: the global traceability or how to feel like an UPS package“, in Information security applications, 2007, Bd. 4298, S. 391–404. doi: 10.1007/978-3-540-71093-6_30.
    [23]
    L. Uhsadel, A. Y. Poschmann, und C. Paar, „Enabling full-size public-key algorithms on 8-bit sensor nodes“, in Security and privacy in ad-hoc and sensor networks, 2007, Bd. 4572, S. 73–86. doi: 10.1007/978-3-540-73275-4_6.
    [24]
    K. Lemke-Rust und C. Paar, „Gaussian mixture models for higher-order side channel analysis“, in Cryptographic hardware and embedded systems – CHES 2007, Wien, 2007, Bd. 4727, S. 14–27. doi: 10.1007/978-3-540-74735-2_2.
    [25]
    Y. Liu, T. Kasper, K. Lemke-Rust, und C. Paar, „E-passport: cracking basic access control keys“, in On the move to meaningful internet systems 2007: CoopIS, DOA, ODBASE, GADA, and IS, 2007, Bd. 4804, S. 1531–1547. doi: 10.1007/978-3-540-76843-2_30.
    [26]
    T. Kasper, D. Carluccio, und C. Paar, „An embedded system for practical security analysis of contactless smartcards“, in Information security theory and practices, 2007, Bd. 4462, S. 150–160. doi: 10.1007/978-3-540-72354-7_13.
    [27]
    A. Y. Poschmann und C. Paar, „Hard­ware op­ti­mier­te Light­weight Block-Chif­fren für RFID- und Sen­sor-Sys­te­me“, in Informatik 2007: Informatik trifft Logistik, Bremen, 2007, Bd. 109 / 110. [Online]. Verfügbar unter: http://www.emsec.rub.de/media/crypto/veroeffentlichungen/2011/01/29/lwc_kryptoitup2007.pdf
    [28]
    C. Paar, A.-R. Sadeghi, J. Schwenk, und C. Wegener, „Studieren mit Sicherheit in Bochum: die Studiengänge zum Thema IT-Sicherheit“, Datenschutz und Datensicherheit, Bd. 31, Nr. 5, S. 338–342, 2007, doi: 10.1007/s11623-007-0130-0.
    [29]
    Y. Liu, T. Kasper, K. Lemke-Rust, und C. Paar, „E-Passport: cracking basic access control keys with Copacobana“, 2007, Publiziert.
    [30]
    K. Lemke-Rust und C. Paar, „Analyzing side channel leakage of masked implementations with stochastic methods“, in Computer security – ESORICS 2007, Dresden, 2007, Bd. 4734, S. 454–468. doi: 10.1007/978-3-540-74835-9_30.
    [31]
    G. Meiser, T. Eisenbarth, K. Lemke-Rust, und C. Paar, „Software implementation of eSTREAM profile: ciphers on embedded 8-bit AVR microcontrollers“, 2007.
    [32]
    Y. Liu, T. Kasper, K. Lemke-Rust, und C. Paar, „E-Passport: cracking basic access control keys with Copacobana“, 2007.
    [33]
    T. Kasper, D. Carluccio, und C. Paar, „An embedded system for practical security analysis of contactless smartcards“, 2007.
    [34]
    K. Lemke-Rust und C. Paar, „Analyzing side channel leakage of masked implementations with stochastic methods“, 2007.
    [35]
    T. Güneysu, C. Paar, und S. Schäge, „Efficient hash collision search strategies on special-purpose hardware“, 2007.
    [36]
    C. Paar und A. Weimerskirch, „Embedded security in a pervasive world“, 2007.
    [37]
    L. Uhsadel, A. Y. Poschmann, und C. Paar, „Enabling full-size public-key algorithms on 8-bit sensor nodes“, 2007.
    [38]
    K. Lemke-Rust und C. Paar, „Gaussian mixture models for higher-order side channel analysis“, 2007.
    [39]
    K. Schramm, N.-G. Leander, P. Felke, und C. Paar, „A collision-attack on AES – combining side channel- and differential-attack“, 2007.
    [40]
    A. Y. Poschmann, N.-G. Leander, K. Schramm, und C. Paar, „New light-weight crypto algorithms for RFID“, 2007.
    [41]
    N.-G. Leander, C. Paar, A. Y. Poschmann, und K. Schramm, „New lightweight DES variants“, 2007.
    [42]
    A. Bogdanov u. a., „Present: an ultra-lightweight block cipher“, Poster-Abstract, 2007
     
    [1]
    C. Paar, „Light-weight cryptography for ubiquitous computing: Securing Cyberspace Workshop IV: Special purpose hardware for Cryptography – Attacks and Applications“, 4. Dezember 2006, Publiziert. [Online]. Verfügbar unter: http://imperia.rz.rub.de:9085/imperia/md/content/texte/publications/selectedtalks/lwc_ucla_dec2006.pdf
    [2]
    C. Paar, S. S. Kumar, J. Pelzl, G. Pfeiffer, und M. Schimmler, „Breaking ciphers with Copacobana: a cost-optimized parallel code breaker or how to break DES for 8,980 €“, 13. Oktober 2006, Publiziert.
    [3]
    S. S. Kumar und C. Paar, „Elliptic curve cryptography for constrained devices“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2006. [Online]. Verfügbar unter: http://www-brs.ub.ruhr-uni-bochum.de/netahtml/HSS/Diss/KumarSandeepS/diss.pdf
    [4]
    C. Paar, „Public-key building blocks: Summer school on cryptographic hardware, side-channel and fault attacks“, 13. Juni 2006, Publiziert. [Online]. Verfügbar unter: http://imperia.rz.rub.de:9085/imperia/md/content/texte/publications/selectedtalks/pk_impl_summer_school_6_2006.pdf
    [5]
    J. Guajardo Merchan, T. Güneysu, S. S. Kumar, C. Paar, und J. Pelzl, „Efficient hardware implementation of finite fields with applications to cryptography“, Acta applicandae mathematicae, Bd. 93, Nr. 1–3, S. 75–118, 2006, doi: 10.1007/s10440-006-9072-z.
    [6]
    K. Lemke-Rust, C. Paar, und A.-R. Sadeghi, „Physical security bounds against tampering“, in Applied cryptography and network security, 2006, Bd. 3989, S. 253–267. doi: 10.1007/11767480_17.
    [7]
    J. Guajardo Merchan, S. S. Kumar, C. Paar, und J. Pelzl, „Efficient software-implementation of finite fields with applications to cryptography“, Acta applicandae mathematicae, Bd. 93, Nr. 1–3, S. 3–32, 2006, doi: 10.1007/s10440-006-9046-1.
    [8]
    S. S. Kumar, C. Paar, J. Pelzl, G. Pfeiffer, und M. Schimmler, „Copacobana – a cost-optimized special-purpose hardware for code-breaking“, in 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2006; FCCM ’06 ; 24 – 26 April 2006, Napa, California ; proceedings, 2006, S. 311–312. doi: 10.1109/fccm.2006.34.
    [9]
    S. S. Kumar, T. Wollinger, und C. Paar, „Optimum digit serial GF(2^m) multipliers for curve based cryptography“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 55, Nr. 10, S. 1306–1311, 2006, doi: 10.1109/tc.2006.165.
    [10]
    A. Y. Poschmann, N.-G. Leander, K. Schramm, und C. Paar, „An efficient block cipher for lightweight cryptosystems“, 2006. [Online]. Verfügbar unter: http://events.iaik.tugraz.at/RFIDSec06/Program/slides/012%20-%20LW%20Block%20Ciphers%20Based%20on%20DES.ppt
    [11]
    S. S. Kumar, C. Paar, J. Pelzl, G. Pfeiffer, und M. Schimmler, „Breaking ciphers with Copacobana: a cost-optimized parallel code breaker“, in Cryptographic hardware and embedded systems – CHES 2006, Yokohama, 2006, Bd. 4249, S. 101–118.
    [12]
    A. Bogdanov, M. C. Mertens, C. Paar, J. Pelzl, und A. Rupp, „A parallel hardware architecture for fast Gaussian elimination over GF(2)“, in 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2006; FCCM ’06 ; 24 – 26 April 2006, Napa, California ; proceedings, 2006, S. 237–246. doi: 10.1109/fccm.2006.12.
    [13]
    S. S. Kumar, C. Paar, J. Pelzl, G. Pfeiffer, A. Rupp, und M. Schimmler, „How to break DES for Euro 8,980“, 2006.
    [14]
    S. S. Kumar, C. Paar, J. Pelzl, G. Pfeiffer, und M. Schimmler, „A configuration concept for a massively parallel FPGA architecture“, 2006.
    [15]
    M. Wolf, A. Weimerskirch, und C. Paar, „Automotive digital rights management systems“, in Embedded security in cars, K. Lemke-Rust, C. Paar, und M. Wolf, Hrsg. Berlin [u.a.]: Springer, 2006, S. 221–232.
    [16]
    M. Wolf, A. Weimerskirch, und C. Paar, „Secure in-vehicle communication“, in Embedded security in cars, K. Lemke-Rust, C. Paar, und M. Wolf, Hrsg. Berlin [u.a.]: Springer, 2006, S. 95–110.
    [17]
    A. Bogdanov, M. C. Mertens, C. Paar, J. Pelzl, und A. Rupp, „A parallel hardware architecture for fast Gaussian elimination over GF(2)“, 2006.
    [18]
    K. Schramm und C. Paar, „Higher order masking of the AES“, 2006. [Online]. Verfügbar unter: http://www.ei.rub.de/forschung/veroeffentlichungen/higher-order-masking-aes-ct-rsa-2006-cryptographer/
    [19]
    T. Güneysu, C. Paar, und J. Pelzl, „On the security of elliptic curve cryptosystems against attacks with special-purpose hardware“, 2006. [Online]. Verfügbar unter: http://www.hyperelliptic.org/tanja/SHARCS/talks06/ecc_rub.pdf
    [20]
    B. Gierlichs, K. Lemke-Rust, und C. Paar, „Templates vs. stochastic methods: a performance analysis for side channel cryptanalysis“, in Cryptographic hardware and embedded systems – CHES 2006, Yokohama, 2006, Bd. 4249, S. 15–29. doi: 10.1007/11894063_2.
    [21]
    K. Lemke-Rust, C. Paar, und M. Wolf, Hrsg., Embedded security in cars: securing current and future automotive IT applications. Berlin [u.a.]: Springer, 2006.
    [22]
    S. S. Kumar und C. Paar, „Are standards compliant elliptic curve cryptosystems feasible on RFID?“, 2006.
    [23]
    A. Weimerskirch und C. Paar, „Generalizations of the Karatsuba algorithm for efficient implementations“, 2006.
    [24]
    K. Lemke-Rust und C. Paar, „Seitenkanal-Analysen: Stand der Forschung in der Methodik“, 2006.
    [25]
    L. Batina u. a., „Testing framework for eSTREAM profile II candidates“, 2006. [Online]. Verfügbar unter: http://www.ecrypt.eu.org/stream/papersdir/2006/014.pdf
    [26]
    D. Carluccio, K. Lemke-Rust, C. Paar, und A.-R. Sadeghi, „E-Passport: the global traceability or How to feel like an UPS package“, 2006, Publiziert.
    [27]
    M. Kasper, S. S. Kumar, K. Lemke-Rust, und C. Paar, „A compact implementation of Edon80“, 2006. [Online]. Verfügbar unter: http://www.ecrypt.eu.org/stream/papersdir/2006/057.pdf
    [28]
    S. S. Kumar, C. Paar, J. Pelzl, G. Pfeiffer, und M. Schimmler, „Breaking ciphers with Copacobana – a cost-optimized parallel code breaker“, 2006.
    [29]
    S. S. Kumar, C. Paar, J. Pelzl, G. Pfeiffer, und M. Schimmler, „Copacobana – a cost-optimized special-purpose hardware for code-breaking“, 2006.
    [30]
    D. Carluccio, K. Lemke-Rust, C. Paar, und A.-R. Sadeghi, „E-passport: the global traceability or how to feel like an UPS package“, 2006.
    [31]
    S. S. Kumar, T. Wollinger, und C. Paar, „Optimum digit serial GF(2^m) multipliers for curve based cryptography“, 2006. [Online]. Verfügbar unter: https://informatik.rub.de/veroeffentlichungen/emsec/2006/pdfs/2006_Optimum_Digit_Serial_GF_2%5Em__Multipliers_for_Curve_Based_Cryptography.pdf
    [32]
    K. Lemke-Rust und C. Paar, „Seitenkanal-Analysen: Stand der Forschung in der Methodik“, in D-A-CH mobility 2006, Ottobrunn, 2006, S. 280–291.
    [33]
    B. Gierlichs, K. Lemke-Rust, und C. Paar, „Templates vs. stochastic methods – a performance analysis for side channel cryptanalysis“, 2006.
    [34]
    T. Wollinger, G. Bertoni, L. Breveglieri, und C. Paar, „Performance of HECC coprocessors using inversion-free formulae“, in Computational science and its applications – ICCSA 2006, Glasgow, 2006, Bd. 3, S. 1004–1012. doi: 10.1007/11751595_105.
    [1]
    T. Wollinger und C. Paar, „Security aspects of FPGAs in cryptographic applications“, in New algorithms, architectures and applications for reconfigurable computing, 2005, S. 265–278. doi: 10.1007/1-4020-3128-9_21.
    [2]
    C. Paar, J. Pelzl, V. Bunimov, M. Schimmler, und D. N. Amanor, „Efficient hardware architectures for modular multiplication on FPGAs“, in Proceedings, 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, 2005, S. 539–542. doi: 10.1109/fpl.2005.1515780.
    [3]
    M. Šimka u. a., „Hardware factorization based on elliptic curve method“, in Proceedings, 13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2005, Napa, CA, 2005, S. 107–116. doi: 10.1109/fccm.2005.40.
    [4]
    A. Weimerskirch, C. Paar, und M. Wolf, „Cryptographic component identification: enabler for secure vehicles“, in VTC 2005-Fall, Dallas, Dallas, 2005, S. 1227–1231. doi: 10.1109/vetecf.2005.1558123.
    [5]
    T. Wollinger, J. Pelzl, und C. Paar, „Cantor versus Harley: optimization and analysis of explicit formulae for hyperelliptic curve cryptosystem“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 54, Nr. 7, S. 861–872, 2005, doi: 10.1109/tc.2005.109.
    [6]
    W. Schindler, K. Lemke-Rust, und C. Paar, „A stochastic model for differential side channel cryptanalysis“, in Cryptographic hardware and embedded systems – CHES 2005, Edinburgh, 2005, Bd. 3659, S. 30–46. doi: 10.1007/11545262_3.
    [7]
    S. Govan, C. Paar, M. MacLoone, und R. Woods, Hrsg., Special issue on cryptographic algorithms and architectures for system-on-chip, Nr. 1. London: IEE, 2005. [Online]. Verfügbar unter: https://digital-library.theiet.org/content/journals/ip-ifs/152/1
    [8]
    H. C. A. van Tilborg und C. Paar, Encyclopedia of cryptography and security. New York: Springer, 2005.
    [9]
    J. Pelzl u. a., „Area-time efficient hardware architecture for factoring integers with the elliptic curve method“, IEE proceedings, Bd. 152, Nr. 1, 2005, doi: 10.1049/ip-ifs:20055018.
    [10]
    H. Kim, T. Wollinger, Y. Choi, K. Chung, und C. Paar, „Hyperelliptic curve coprocessors on a FPGA“, in Information security applications, 2005, Bd. 3325, S. 360–374. doi: 10.1007/978-3-540-31815-6_29.
    [11]
    T. Wollinger, G. Bertoni, L. Breveglieri, und C. Paar, „Performance of HECC coprocessors using inversionfree formulae“, 2005.
    [12]
    A. J. Elbirt und C. Paar, „An instruction-level distributed processor for symmetric-key cryptography“, IEEE transactions on parallel and distributed systems, Bd. 16, Nr. 5, S. 468–480, 2005, doi: 10.1109/tpds.2005.51.
    [13]
    J. Franke, T. Kleinjung, C. Paar, J. Pelzl, C. Priplata, und C. Stahlke, „SHARK : a realizable special hardware sieving device for factoring 1024-bit integers“, in Cryptographic hardware and embedded systems – CHES 2005, Edinburgh, 2005, Bd. 3659, S. 119–130. doi: 10.1007/11545262_9.
    [14]
    C. Castelluccia, H. Hartenstein, C. Paar, und D. Westhoff, Hrsg., Security in ad hoc and sensor networks: first European workshop ; revised selected papers; ESAS 2004, Heidelberg, Germany, August 6, 2004. Claude Castelluccia … (eds.). Berlin [u.a.]: Springer, 2005.
    [15]
    C. Paar, M. Wolf, und A. Weimerskirch, „Digital rights management Systeme (DRMS) als enabling technology im Automobil“, in Sicherheit 2005, 2005, Bd. 62, S. 193–196. [Online]. Verfügbar unter: http://weimerskirch.org/papers/WolfEtAl_DRMSCar.pdf
    [16]
    J. Franke u. a., „An efficient hardware architecture for factoring large numbers with the elliptic curve method“, 2005.
    [17]
    A. J. Elbirt und C. Paar, „An instruction-level distributed processor for symmetric-key cryptography“, 2005.
    [18]
    T. Wollinger, J. Pelzl, und C. Paar, „Cantor versus Harley: optimization and analysis of explicit formulae for hyperelliptic curve cryptosystem“, 2005.
    [1]
    A. Weimerskirch, C. Paar, und J.-P. Hubaux, „Authentication in Ad-hoc and sensor networks“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2004. [Online]. Verfügbar unter: https://hss-opus.ub.ruhr-uni-bochum.de/opus4/frontdoor/deliver/index/docId/544/file/diss.pdf
    [2]
    J. Guajardo Merchan und C. Paar, „Arithmetic architectures for finite fields GF(pm) with cryptographic applications“, Universitätsbibliothek, Ruhr-Universität Bochum, Bochum, 2004. [Online]. Verfügbar unter: http://www-brs.ub.ruhr-uni-bochum.de/netahtml/HSS/Diss/GuajardoMerchanJorge/diss.pdf
    [3]
    J. Großschädl, S. S. Kumar, und C. Paar, „Architectural support for arithmetic in optimal extension fields“, in Proceedings, 2004, S. 111–124. doi: 10.1109/asap.2004.1342463.
    [4]
    T. Wollinger, J. Guajardo Merchan, und C. Paar, „Security on FPGAs: State-of-the-art implementations and attacks“, ACM transactions on embedded computing systems, Bd. 3, Nr. 3, S. 534–574, 2004, doi: 10.1145/1015047.1015052.
    [5]
    J. Pelzl, T. Wollinger, und C. Paar, „High performance arithmetic for special hyperelliptic curve cryptosystems of genus two“, in ITCC 2004 : International Conference on Information Technology, Coding and Computing , Las Vegas, Nevada , 2004, S. 513–517. doi: 10.1109/itcc.2004.1286706.
    [6]
    T. Wollinger, J. Pelzl, V. Wittelsberger, C. Paar, G. Saldamli, und Ç. K. Koç, „Elliptic and hyperelliptic curves on embedded μP“, ACM transactions on embedded computing systems, Bd. 3, Nr. 3, S. 509–533, 2004, doi: 10.1145/1015047.1015051.
    [7]
    S. S. Kumar und C. Paar, „Reconfigurable instruction set extension for enabling ECC on an 8-bit processor“, in Field programmable logic and applications, Antwerpen, 2004, Bd. 3203, S. 586–595. doi: 10.1007/978-3-540-30117-2_60.
    [8]
    S. Baktir, J. Pelzl, T. Wollinger, B. Sunar, und C. Paar, „Optimal tower fields for hyperelliptic curve cryptosystems“, in Conference record of the thirty-eighth Asilomar conference on signals, systems & computers, Pacific Grove, Ca, 2004, S. 522–527.
    [9]
    C. Paar, J. Pelzl, K. Schramm, A. Weimerskirch, und T. Wollinger, „Eingebettete Sicherheit: state-of-the-art“, 2004.
    [10]
    K. Schramm, N.-G. Leander, P. Felke, und C. Paar, „A collision-attack on AES – combining side channel- and differential-attack“, in Cryptographic hardware and embedded systems – CHES 2004, Cambridge, Mass., 2004, Bd. 3156, S. 163–175. doi: 10.1007/978-3-540-28632-5_12.
    [11]
    K. Lemke-Rust, K. Schramm, und C. Paar, „DPA on n-bit sized boolean and arithmetic operations and its application to IDEA, RC6 and the HMAC-construction“, in Cryptographic hardware and embedded systems – CHES 2004, Cambridge, Mass., 2004, Bd. 3156, S. 205–219. doi: 10.1007/978-3-540-28632-5_15.
    [12]
    J. Pelzl, T. Wollinger, und C. Paar, „Low cost security: explicit formulae for genus-4 hyperelliptic curves“, in Selected areas in cryptography, 2004, Bd. 3006, S. 1–16. doi: 10.1007/978-3-540-24654-1_1.
    [13]
    G. Bertoni, L. Breveglieri, T. Wollinger, und C. Paar, „Finding optimum parallel coprocessor design for genus 2 hyperelliptic curve cryptosystems“, in ITCC 2004 : International Conference on Information Technology, Coding and Computing , Las Vegas, Nevada , 2004, S. 538–544. doi: 10.1109/itcc.2004.1286710.
    [14]
    C. Paar, „Embedded security in Automobilanwendungen“, Elektronik automotive, Nr. 1, S. 1–6, 2004.
    [15]
    E. Barteska, C. Paar, J. Pelzl, V. Wittelsberger, und T. Wollinger, „Case study: compiler comparison for an embedded cryptographical application“, in Proceedings of the International conference on embedded systems and applications ESA ’04 and proceedings of the International conference on VLSI, Las Vegas, Nevada, 2004, S. 589–595.
    [16]
    S. S. Kumar, K. Lemke-Rust, und C. Paar, „Some thoughts about implementation properties of stream ciphers“, 2004.
    [17]
    M. Wolf, A. Weimerskirch, und C. Paar, „Security in automotive bus systems“, 2004. [Online]. Verfügbar unter: http://weimerskirch.org/papers/WolfEtAl_SecureBus.pdf
    [18]
    M. Wolf, A. Weimerskirch, und C. Paar, „Sicherheit in automobilen Bussystemen“, in Automotive – safety & security 2004, 2004, S. 9–20.
    [19]
    K. Schramm, N.-G. Leander, P. Felke, und C. Paar, „A collision-attack on AES – combining side channel- and differential-attack“, 2004.
    [20]
    J. Großschädl, S. S. Kumar, und C. Paar, „Architectural support for arithmetic in optimal extension fields“, 2004.
    [21]
    E. Barteska, C. Paar, J. Pelzl, V. Wittelsberger, und T. Wollinger, „Case study: compiler comparison for an embedded cryptographical application“, 2004.
    [22]
    K. Lemke-Rust, K. Schramm, und C. Paar, „DPA on n-bit sized boolean and arithmetic operations and its application to IDEA, RC6 and the HMAC-construction“, 2004.
    [23]
    C. Paar, J. Pelzl, K. Schramm, A. Weimerskirch, und T. Wollinger, „Eingebettete Sicherheit: state-of-the-art“, in D-A-CH Security 2004, Basel, 2004, S. 349–363.
    [24]
    J. Pelzl, T. Wollinger, und C. Paar, „High performance arithmetic for special hyperelliptic curve cryptosystems of genus two“, 2004.
    [25]
    S. S. Kumar und C. Paar, „Reconfigurable instruction set extension for enabling ECC on an 8-bit processor“, 2004.
    [26]
    T. Wollinger und C. Paar, „Security aspects of FPGAs in cryptographic applications“, 2004.
    [1]
    C. Paar, „Pervasive computing and the future of crypto engineering“, 15. Dezember 2003, Publiziert. [Online]. Verfügbar unter: http://imperia.rz.rub.de:9085/imperia/md/content/texte/publications/talks/pervasive_crypto_epfl_12_2003.pdf
    [2]
    C. Paar, „Past and future of cryptographic engineering“, 18. August 2003, Publiziert. [Online]. Verfügbar unter: http://imperia.rz.rub.de:9085/imperia/md/content/texte/publications/talks/hotchips2003_crypto_tutorial.pdf
    [3]
    C. Paar, J. Pelzl, und T. Wollinger, „Hyperelliptic curve cryptosystems for embedded applications“, Aug. 2003. [Online]. Verfügbar unter: https://www.emsec.ruhr-uni-bochum.de/media/crypto/attachments/files/vortrag/ecc03paar.pdf
    [4]
    C. Paar und C. K. Koc, Hrsg., Special issue on cryptographic hardware and embedded system, Nr. 4. 2003. [Online]. Verfügbar unter: http://ieeexplore.ieee.org/xpl/tocresult.jsp?isnumber=26688&punumber=12
    [5]
    J. Pelzl, T. Wollinger, C. Paar, und J. Guajardo Merchan, „Hyperelliptic curve cryptosystems: closing the performance gap to elliptic curves“, in Cryptographic Hardware and Embedded Systems – CHES 2003, Köln, 2003, Bd. 2779, S. 351–365. doi: 10.1007/978-3-540-45238-6_28.
    [6]
    S. S. Kumar, M. Girimondo, A. Weimerskirch, C. Paar, A. Patel, und A. S. Wander, „Embedded end-to-end wireless security with ECDH key exchange“, in Proceedings of the 46th IEEE international midwest symposium on circuits & systems, 2003, S. 786–789. doi: 10.1109/mwscas.2003.1562404.
    [7]
    T. Wollinger, J. Guajardo Merchan, und C. Paar, Hrsg., Cryptography on FPGAs: state of the art implementations and attacks, Nr. 3. 2003.
    [8]
    T. Wollinger und C. Paar, „How secure are FPGAs in cryptographic applications?“, in Field programmable logic and applications, 2003, Bd. 2778, S. 91–100. doi: 10.1007/978-3-540-45234-8_10.
    [9]
    T. Wollinger, J. Guajardo Merchan, und C. Paar, „Security on FPGAs: state of the art implementations and attacks“, ACM transactions on embedded computing systems, Bd. 3, Nr. 3, 2003.
    [10]
    C. D. Walter, Ç. K. Koç, und C. Paar, Hrsg., Cryptographic Hardware and Embedded Systems – CHES 2003: 5th international workshop, Cologne, Germany, September 8 – 10, 2003 ; proceedings. Berlin [u.a.]: Springer, 2003. doi: 10.1007/978-3-540-45238-6.
    [11]
    G. Bertoni, J. Guajardo Merchan, S. S. Kumar, G. Orlando, C. Paar, und T. Wollinger, „Efficient GF(pm) arithmetic architectures for cryptographic applications“, in Topics in cryptology, Bd. 2612, M. Joye, Hrsg. Berlin: Springer, 2003, S. 158–175. doi: 10.1007/3-540-36563-x_11.
    [12]
    B. S. Kaliski, Ç. K. Koç, und C. Paar, Hrsg., Cryptographic Hardware and Embedded Systems – CHES 2002: 4th International Workshop Redwood Shores, CA, USA, August 13-15, 2002 ; revised papers. Berlin [u.a.]: Springer, 2003. doi: 10.1007/3-540-36400-5.
    [13]
    K. Schramm, T. Wollinger, und C. Paar, „A new class of collision attacks and its application to DES“, in Fast software encryption, 2003, Bd. 2887, S. 206–222. doi: 10.1007/978-3-540-39887-5_16.
    [14]
    T. Wollinger, J. Guajardo Merchan, und C. Paar, „Cryptography in embedded systems: an overview“, in Vorträge und Begleittexte zur embedded world 2003 conference, 2003, S. 735–744.
    [15]
    C. Paar und T. Wollinger, „Eingebettete Sicherheit und Kryptographie im Automobil: eine Einführung“, in Innovative Informatikanwendungen, 2003, Bd. 34, S. 325–329. [Online]. Verfügbar unter: http://subs.emis.de/LNI/Proceedings/Proceedings34/GI-Proceedings.34-54.pdf
    [16]
    T. Wollinger, J. Guajardo Merchan, und C. Paar, Vorträge und Begleittexte zur embedded world 2003 conference: Grundlagen, Architekturen, Werkzeuge und Lösungen ; 18. – 20. Februar 2003 in Nürnberg. 2003.
    [17]
    T. Wollinger und C. Paar, „How secure are FPGAs in cryptographic applications?: Long Version“, 2003.
    [18]
    K. Schramm, T. Wollinger, und C. Paar, „A new class of collision attacks and its application to DES“, 2003.
    [1]
    J. Guajardo Merchan, T. Wollinger, und C. Paar, Conference proceedings: the 2002 45th Midwest Symposium on Circuits and Systems : August 4 – 7, 2002, Tulsa, Oklahoma / co-sponsored by the IEEE Circuits and Systems Society and the School of Electrical and Computer Engineering at Oklahoma State University. Piscataway, NJ: IEEE Computer Society Press, 2002.
    [2]
    T. Wollinger und C. Paar, „Hardware architectures proposed for cryptosystems based on hyperelliptic curves“, in The 9th IEEE international conference on electronics circuits and systems, 2002, S. 1159–1162.
    [3]
    J. Guajardo Merchan, T. Wollinger, und C. Paar, „Area efficient GF(p) architectures for GF(p(m)) multipliers“, in Conference proceedings, 2002, S. 37–40.
    [4]
    J. Guajardo Merchan und C. Paar, „Itoh-Tsujii inversion in standard basis and its application in cryptography and codes“, Designs, codes and cryptography, Bd. 25, Nr. 2, S. 207–216, 2002.
    [5]
    H. Dobbertin und C. Paar, „“Code knacken” aus Profession“, Rubin Sonderheft, Nr. 2, S. 6–14, 2002, [Online]. Verfügbar unter: http://www.ruhr-uni-bochum.de/rubin/rbin2_02/pdf/dobbertin.pdf
    [1]
    T. Blum und C. Paar, „High radix Montgomery modular exponentiation on reconfigurable hardware“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 50, Nr. 7, S. 759–764, 2001, doi: 10.1109/12.936241.
    [2]
    Ç. K. Koç, D. Naccache, und C. Paar, Hrsg., Cryptographic hardware and embedded systems – CHES 2001: third international workshop Paris, France, May 14-16, 2001 ; proceedings. Berlin: Springer, 2001. doi: 10.1007/3-540-44709-1.
    [3]
    G. Orlando und C. Paar, „A scalable GF(p) elliptic curve processor architecture for programmable hardware“, in Cryptographic hardware and embedded systems – CHES 2001, Paris, 2001, Bd. 2162, S. 348–363. doi: 10.1007/3-540-44709-1_29.
    [4]
    A. J. Elbirt, W. Yip, B. R. Chetwynd, und C. Paar, „An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists“, IEEE transactions on very large scale integration (VLSI) systems / Institute of Electrical and Electronics Engineers, Bd. 9, Nr. 4, S. 545–557, 2001, doi: 10.1109/92.931230.
    [5]
    J. Guajardo Merchan, R. Blümel, U. Krieger, und C. Paar, „Efficient implementation of elliptic curve cryptosystems on the TI MSP430x33x family of microcontrollers“, in Public key cryptography, Jeju, 2001, Bd. 1992, S. 365–382. doi: 10.1007/3-540-44586-2_27.
    [6]
    D. V. Bailey und C. Paar, „Efficient arithmetic in finite field extensions with application in elliptic curve cryptography“, Journal of cryptology, Bd. 14, Nr. 3, S. 153–176, 2001, doi: 10.1007/s001450010012.
    [7]
    A. Weimerskirch, C. Paar, und S. Chang Shantz, „Elliptic curve cryptography on a Palm OS device“, in Information security and privacy, Sydney, 2001, Bd. 2119, S. 502–513. doi: 10.1007/3-540-47719-5_39.
    [8]
    A. J. Elbirt, W. Yip, B. R. Chetwynd, und C. Paar, „An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists“, 2001.
    [9]
    D. V. Bailey und C. Paar, „Efficient arithmetic in finite field extensions with application in elliptic curve cryptography“, 2001.
    [10]
    T. Blum und C. Paar, „High radix Montgomery modular exponentiation on reconfigurable hardware“, 2001.
    [1]
    C. Paar, „Reconfigurable hardware in modern cryptography“, 6. Oktober 2000, Publiziert. [Online]. Verfügbar unter: http://imperia.rz.rub.de:9085/imperia/md/content/texte/publications/talks/paar_ecc2000.pdf
    [2]
    Ç. K. Koç und C. Paar, Hrsg., Cryptographic hardware and embedded systems – CHES 2000: second international workshop Worcester, MA, USA, August 17-18, 2000 ; proceedings. Berlin: Springer, 2000. doi: 10.1007/3-540-44499-8.
    [3]
    A. J. Elbirt und C. Paar, „An FPGA implementation and performance evaluation of the Serpent block cipher“, in FPGA ’00, Monterey, CA, 2000, S. 33–40. doi: 10.1145/329166.329176.
    [4]
    G. Orlando und C. Paar, „A high-performance reconfigurable elliptic curve processor for GF(2m)“, in Cryptographic hardware and embedded systems – CHES 2000, Worcester, Mass., 2000, Bd. 1965, S. 41–56. doi: 10.1007/3-540-44499-8_3.
    [5]
    A. D. Woodbury, D. V. Bailey, und C. Paar, „Elliptic curve cryptography on smart cards without coprocessors“, in Smart card research and advanced applications, Bristol, 2000, Bd. 52, S. 71–92. doi: 10.1007/978-0-387-35528-3_5.
    [6]
    T. Wollinger, M. Wang, J. Guajardo Merchan, und C. Paar, „How well are high-end DSPs suited for the AES algorithms?: AES algorithms on the TMS320C6x DSP“, 2000.
    [7]
    G. Orlando und C. Paar, „Squaring architecture for GF(2m) and its applications in cryptographic systems“, Electronics letters, Bd. 36, Nr. 13, S. 1116–1117, Juni 2000, doi: 10.1049/el:20000824.
    [8]
    A. J. Elbirt, W. Yip, B. R. Chetwynd, und C. Paar, „An FPGA implementation and performance evaluation of the AES block cipher candidate algorithm finalists“, 2000.
    [9]
    G. Orlando und C. Paar, „A high-performance reconfigurable elliptic curve processor for GF(2m)“, 2000.
    [10]
    G. Orlando und C. Paar, „Efficient squaring architecture for GF(2m) and its applications in cryptographic systems“, 2000.
    [1]
    C. Paar, „Implementation options for finite field arithmetic for elliptic curve cryptosystems“, 2. November 1999, Publiziert.
    [2]
    C. Paar, P. Fleischmann, und P. Soria-Rodriguez, „Fast arithmetic for public-key algorithms in Galois fields with composite exponents“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 48, Nr. 10, S. 1025–1034, 1999, doi: 10.1109/12.805153.
    [3]
    C. Paar, B. R. Chetwynd, T. J. Connor, S. Y. Deng, und S. J. Marchant, „An algorithm-agile cryptographic co-processor based on FPGAs“, in Reconfigurable technology: FPGAs for computing and applications, Boston, Mass., 1999, Bd. 3844, S. 11–16. doi: 10.1117/12.359537.
    [4]
    T. Blum und C. Paar, „Montgomery modular multiplication on reconfigurable hardware“, in Proceedings / 14th IEEE Symposium on Computer Arithmetic : April 14 – 16, 1999, Adelaide, Australia, 1999, S. 70–77.
    [5]
    Ç. K. Koç und C. Paar, Hrsg., Cryptographic hardware and embedded systems: first international workshop, CHES ’99, Worcester, MA, USA, August 12 – 13, 1999 ; proceedings. Berlin [u.a.]: Springer, 1999. doi: 10.1007/3-540-48059-5.
    [6]
    D. V. Bailey, W. Cammack, J. Guajardo Merchan, und C. Paar, „Cryptography in modern communication systems“, 1999.
    [7]
    T. Blum und C. Paar, Proceedings / 14th IEEE Symposium on Computer Arithmetic : April 14 – 16, 1999, Adelaide, Australia. Los Alamitos: IEEE, 1999.
    [8]
    C. Paar, „Algorithmenunabhängige Krypto-Hardware: moderne Sicherheitsprotokolle erfordern den Wechsel zwischen kryptographischen Algorithmen“, Datenschutz und Datensicherheit, Bd. 23, Nr. 10, S. 562–564, 1999.
    [9]
    J.-P. Kaps und C. Paar, „DES auf FPGAs: Hochgeschwindigkeits-Architekturen für den Data Encryption Standard auf rekonfigurierbarer Hardware.“, Datenschutz und Datensicherheit, Bd. 23, Nr. 10, S. 565–569, 1999.
    [10]
    A. J. Elbirt und C. Paar, „Towards an FPGA architecture optimized for public-key algorithms“, in Reconfigurable technology: FPGAs for computing and applications, Boston, Mass., 1999, Bd. 3844, S. 33–42. [Online]. Verfügbar unter: https://spie.org/Publications/Proceedings/Paper/10.1117/12.359540
    [11]
    G. Orlando und C. Paar, „A super-serial Galois fields multiplier for FPGAs and its application to public-key algorithms“, in Proceedings / Seventh annual IEEE symposium on field-programmable custom computing machines, FCCM ’99, : April 21 – 23, 1999, Napa Valley, California, 1999, S. 232–239. doi: 10.1109/fpga.1999.803685.
    [12]
    J.-P. Kaps und C. Paar, „Fast DES implementation for FPGAs and its application to a universal key-search machine“, in Selected Areas in Cryptography, Kingston, Ontario, 1999, Bd. 1556, S. 234–247.
    [13]
    C. Paar, B. R. Chetwynd, T. J. Connor, S. Y. Deng, und S. J. Marchant, „An algorithm-agile cryptographic co-processor based on FPGAs“, 1999.
    [14]
    D. V. Bailey, W. Cammack, J. Guajardo Merchan, und C. Paar, „Cryptography in modern communication systems“, in DSPS Fest ’99, Houston, TX, 1999, Publiziert. [Online]. Verfügbar unter:     http://www.ti.com/sc/docs/general/dsp/fest99/wireless/5wpi.pdf
    [15]
    C. Paar, P. Fleischmann, und P. Soria-Rodriguez, „Fast arithmetic for public-key algorithms in Galois fields with composite exponents“, 1999.
    [1]
    C. Paar, P. Fleischmann, und P. Roelse, „Efficient multiplier architectures for Galois fields GF(2(4n))“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 47, Nr. 2, S. 162–170, 1998, doi: 10.1109/12.663762.
    [2]
    D. V. Bailey und C. Paar, „Optimal extension fields for fast arithmetic in public-key algorithms“, in Advances in cryptology – CRYPTO ’98, Santa Barbara, CA, 1998, Bd. 1462, S. 472–485. doi: 10.1007/bfb0055748.
    [3]
    J. Guajardo Merchan und C. Paar, „Fast inversion in composite Galois fields GF((2n)m)“, in Proceedings / 1998 IEEE International Symposium on Information Theory : MIT, Cambridge, MA, USA, 16 – 21 August 1998, 1998, Publiziert.
    [1]
    G. Haskins, C. Paar, und S. Dempsey, „Securing ATM“, 28. Januar 1997, Publiziert.
    [2]
    C. Paar und P. Soria-Rodriguez, „Fast arithmetic architectures for public-key algorithms over Galois fields GF ((2n)m)“, in Advances in cryptology, 1997, Bd. 1233, S. 363–378. doi: 10.1007/3-540-69053-0_25.
    [3]
    C. Paar und M. Rosner, „Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardware“, in Proceedings / the 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines : April 16 – 18, 1997, Napa Valley, California, 1997, S. 219–225.
    [4]
    C. Paar und J. Guajardo Merchan, „Efficient algorithms for elliptic curve cryptosystems“, in Advances in cryptology, 1997, Bd. 1294, S. 342–356.
    [5]
    J. L. Fan und C. Paar, Hrsg., Proceedings / 1997 IEEE International symposium on information theory: Maritim Hotel and Congress Center, Ulm, Germany, June 29 – July 4, 1997 sponsored by the information theory society of the institute of electrical and electronics engineers. Piscataway, NJ: IEEE, 1997.
    [6]
    C. Paar, „Optimized arithmetic for Reed-Solomon encoders“, in Proceedings / 1997 IEEE International symposium on information theory, 1997, S. 250. doi: 10.1109/isit.1997.613165.
    [7]
    J. L. Fan und C. Paar, „On efficient inversion in tower fields of characteristic two“, in Proceedings / 1997 IEEE International symposium on information theory, 1997, S. 20.
    [1]
    C. Paar, „A new architecture for a parallel finite field multiplier with low complexity based on composite fields“, IEEE transactions on computers / Institute of Electrical and Electronics Engineers, Bd. 45, Nr. 7, S. 856–861, 1996, doi: 10.1109/12.508323.
    [2]
    G. Pierce und C. Paar, „Recent developments in digital wireless network security“, 1996.
    [1]
    C. Paar, „Some remarks on efficient inversion in finite fields“, in Proceedings / 1995 IEEE international symposium on information theory, 1995, S. 58. doi: 10.1109/isit.1995.531160.
    [2]
    C. Paar, Proceedings / 1995 IEEE international symposium on information theory: Whistler conference center, Whistler, British Columbia, Canada, 17 – 22 September, 1995. Piscataway, NJ: IEEE Computer Society Press, 1995.
    [3]
    C. Paar und N. Lange, „A comparative VLSI synthesis of finite field multipliers“, 1995. [Online]. Verfügbar unter: http://www.researchgate.net/publication/2624309_A_Comparative_VLSI_Synthesis_of_Finite_Field_Multipliers
    [1]
    C. Paar und O. Hooijen, „Implementation of a reprogrammable Reed-Solomon decoder over GF(2^16) on a digital signal processor with external arithmetic unit“, 1994. [Online]. Verfügbar unter: http://www.ei.rub.de/media/crypto/veroeffentlichungen/2011/01/18/esa.ps
    [2]
    C. Paar, „Low complexity parallel multipliers for Galois fields GF((2n)4) based on special types of primitive polynomials“, 1994, Publiziert.

    Publications

    20 Einträge « ‹ 1 von 2 › »

    Alexander May, Massimo Ostuzzi

    Multiple Group Action Dlogs with(out) Precomputation Artikel Geplante Veröffentlichung

    In: Preprint, Geplante Veröffentlichung.

    Links | Schlagwörter: Preprint

    Sebastian Bitzer, Jeroen Delvaux, Elena Kirshanova, Sebastian Maaßen, Alexander May, Antonia Wachter-Zeh

    How to Lose Some Weight - A Practical Template Syndrome Decoding Attack Workshop

    Coding and Cryptography (WCC 24), 2024.

    Links | Schlagwörter: Crypto Others

    Alexander May, Julian Nowakowski

    Too Many Hints - When LLL Breaks LWE Proceedings Article

    In: Advances in Cryptology (ASIACRYPT 23), 2023.

    Links | Schlagwörter: Crypto Flagship, Rank A*/A

    Timo Glaser, Alexander May

    How to Enumerate LWE Keys as Narrow as in Kyber/Dilithium Proceedings Article

    In: Cryptology and Network Security (CANS 23), S. 75–100, Springer, 2023.

    Links | Schlagwörter: Crypto Others

    Elena Kirshanova, Alexander May

    Breaking Goppa-based McEliece with hints Proceedings Article

    In: Security and Cryptography for Networks (SCN 22), and Journal of Information and Computation, Volume 293, 2023.

    Links | Schlagwörter: Crypto Others

    Jesús-Javier Chi-Dominguez, Andre Esser, Sabrina Kunzweiler, Alexander May

    Low Memory Attacks on Small Key CSIDH Proceedings Article

    In: Applied Cryptography and Network Security (ACNS 23), S. 276–304, Springer, 2023.

    Links | Schlagwörter: Crypto Others

    Elena Kirshanova, Alexander May, Julian Nowakowski

    New NTRU Records with Improved Lattice Bases Proceedings Article

    In: Post-Quantum Cryptography (PQCrypto 23), S. 167–195, Springer, 2023.

    Links | Schlagwörter: Crypto Others

    Alexander May, Carl Richard Theodor Schneider

    Dlog is Practically as Hard (or Easy) as DH - Solving Dlogs via DH Oracles on EC Standards Proceedings Article

    In: Transactions on Cryptographic Hardware and Embedded Systems (TCHES), S. 146–166, 2023.

    Links | Schlagwörter: Crypto Area, Rank A*/A

    Andre Esser, Alexander May, Javier A. Verbel, Weiqiang Wen

    Partial Key Exposure Attacks on BIKE, Rainbow and NTRU Proceedings Article

    In: Advances in Cryptology (CRYPTO 2022) , S. 346–375, Springer, 2022.

    Links | Schlagwörter: Crypto Flagship, Rank A*/A

    Alexander May, Julian Nowakowski, Santanu Sarkar

    Approximate Divisor Multiples - Factoring with Only a Third of the Secret CRT-Exponents Proceedings Article

    In: Advances in Cryptology (EUROCRYPT 22) , S. 147–167, Springer, 2022.

    Links | Schlagwörter: Crypto Flagship, Rank A*/A

    20 Einträge « ‹ 1 von 2 › »

    Memberships

    • BITSI – Bochumer Verein zur Förderung der IT-Sicherheit und Informatik
    • CASA – DFG Excellence Cluster
    • QSI – EU Marie Curie Network
    • HGI – Horst Görtz Institute
    • IACR – Cryptology Research

    Lectures (Moodle/Notes)

    Crypto Challenges

    Former PhDs

    1. Önder Askin, 2024
    2. Floyd Zweydinger, 2023
    3. Lars Schlieper, 2022
    4. Alexander Helm, 2020
    5. Andre Esser, 2020
    6. Matthias Minihold, 2019 
    7. Leif Both, 2018
    8. Robert Kübler, 2018
    9. Elena Kirshanova, 2016
    10. Ilya Ozerov, 2016
    11. Gottfried Herold, 2014
    12. Alexander Meurer, 2014
    13. Mathias Herrmann, 2011
    14. Maike Ritzenhofen, 2010

    Calvin & Hobbes