2nd Workshop on
Low-Latency Encryption
(LLE 2025)

In recent years, the demand for cryptographic primitives with minimum execution time has greatly increased. Memory encryption, secure cache architectures and pointer authentication are among the most commonly cited use cases for cryptographic algorithms that feature a low latency in hardware, i.e., a short period between providing inputs and receiving outputs. While execution speed is clearly the main criterion for such designs, other factors such as area, power and energy consumption have to be considered as well. Arguably the most challenging aspect of designing dedicated low-latency primitives is that there is very little room for error in the security analysis. Considerable safety margins to account for uncertainties or potential improvements of attacks are hardly affordable, bold security claims and careful public scrutiny are needed. Hence, the concrete trade-offs between hardware implementation parameters and cryptanalytic properties need to be well understood to find designs with optimal performance for a desired security level.