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  6. Prof. Dr. Amir Mo­ra­di

Prof. Dr. Amir Mo­ra­di

Implementation Security

Adresse:
Ruhr-Universität Bochum
Fakultät für Informatik
Implementation Security
Universitätsstraße 150
D-44801 Bochum

Raum: ID 2/605

Telefon: +49 (0)234 32-27219

Sprechzeiten: Nach Absprache

E-Mail: amir.moradi@rub.de

©RUB, Marquard

Vita

  • Since 8/2022: W2 Pro­fes­sor for Implementation Security
    Fa­cul­ty of Computer Science, Ruhr-Uni­ver­si­tät Bo­chum, Ger­ma­ny

  • 10/2021-8/2022: W2 Pro­fes­sor for IT-Se­cu­ri­ty
    In­sti­tu­te of Com­pu­ter Sci­ence, Uni­ver­si­ty of Co­lo­gne, Ger­ma­ny

  • 4/2021-10/2021: Ex­tra­or­di­na­ry Pro­fes­sor (Au­ßer­plan­mä­ßi­ger Pro­fes­sor)
    Fa­cul­ty of Elec­tri­cal En­gi­nee­ring and In­for­ma­ti­on Sci­en­ces, Ruhr-Uni­ver­si­tät Bo­chum, Ger­ma­ny

  • 1/2020-10/2021: Aca­de­mic Coun­cilor (Aka­de­mi­scher Rat)
    Se­cu­ri­ty En­gi­nee­ring, Ruhr-Uni­ver­si­tät Bo­chum, Ger­ma­ny

  • 2016-2019: Aca­de­mic Coun­cilor (Aka­de­mi­scher Rat)
    Em­bed­ded Se­cu­ri­ty, Ruhr-Uni­ver­si­tät Bo­chum, Ger­ma­ny

  • 10/2015-4/2021: Fa­cul­ty Mem­ber (Pri­vat­do­zent)
    Fa­cul­ty of Elec­tri­cal En­gi­nee­ring and In­for­ma­ti­on Sci­en­ces, Ruhr-Uni­ver­si­tät Bo­chum, Ger­ma­ny

  • 2015: Ha­bi­li­ta­ti­on in Em­bed­ded Se­cu­ri­ty (Ad­van­ces in Si­de-Chan­nel Se­cu­ri­ty)
    Ruhr-Uni­ver­si­tät Bo­chum, Ger­ma­ny

  • 2009-2016: post-doc­to­ral re­se­ar­cher
    Em­bed­ded Se­cu­ri­ty, Ruhr-Uni­ver­si­tät Bo­chum, Ger­ma­ny

  • 2008: PhD in Com­pu­ter En­gi­nee­ring
    Sharif Uni­ver­si­ty of Tech­no­lo­gy, Tehr­an, Iran

  • 2007-2008: vi­sit­ing PhD stu­dent
    Em­bed­ded Se­cu­ri­ty, Ruhr-Uni­ver­si­tät Bo­chum, Ger­ma­ny

  • 2004: MSc in Com­pu­ter En­gi­nee­ring
    Sharif Uni­ver­si­ty of Tech­no­lo­gy, Tehr­an, Iran

  • 2001: BSc in Com­pu­ter En­gi­nee­ring
    Shahid Be­hesh­ti Uni­ver­si­ty, Tehr­an, Iran

Re­se­arch

  • Topics

    • Implementation Security
    • Si­de-Chan­nel Analysis and Countermeasures
    • Fault-Injection Attacks and Countermeasures
    • Ef­fi­ci­ent Im­ple­men­ta­ti­on of Cryp­to­gra­phic Primitives
    • Applied Cryptography
  • Profiles

Awards/Ho­nors

  • Awarded by 100,000 € (1st place) in the 9th German IT Security Award 2022, announcement.
  • Highest number of publications at CHES in one year for the entire history of CHES, with 10 publications at CHES 2021, announcement.
  • Currently the 2nd prolific author of CHES.
  • Highest number of publications at CHES 2022 with 8 papers, announcement.
  • Dis­tin­gu­is­hed Paper award at USE­NIX Se­cu­ri­ty Sym­po­si­um – USE­NIX 2020.
  • Best paper award at Con­fe­rence on Cryp­to­gra­phic Hard­ware and Em­bed­ded Sys­tems – CHES 2019.
  • Co-aut­hor of the Best Stu­dent-Pa­per Award at IEEE In­ter­na­tio­nal Sym­po­si­um on Hard­ware Ori­en­ted Se­cu­ri­ty and Trust – HOST 2016.
  • Best Pa­per Award at In­ter­na­tio­nal Work­shop on Con­struc­tive Si­de-Chan­nel Ana­ly­sis and Se­cu­re De­sign – CO­SA­DE 2015.
  • Co-aut­hor of the Best Stu­dent-Pa­per Award at In­ter­na­tio­nal Con­fe­rence on Ap­p­lied Cryp­to­gra­phy and Net­work Se­cu­ri­ty – ACNS 2014.
  • No­mi­na­ted for the best paper award at De­sign, Au­to­ma­ti­on & Test in Eu­ro­pe Con­fe­rence & Ex­hi­bi­ti­on – DATE 2018.
  • No­mi­na­ted for the best paper award at De­sign, Au­to­ma­ti­on & Test in Eu­ro­pe Con­fe­rence & Ex­hi­bi­ti­on – DATE 2017.
  • No­mi­na­ted for the best paper award at Work­shop on Cryp­to­gra­phic Hard­ware and Em­bed­ded Sys­tems – CHES 2015.

Pro­gram Com­mit­tee Mem­bership

Edi­to­ri­al Board Mem­bership

  • PC co-chair of Smart Card Re­se­arch and Ad­van­ced Ap­p­li­ca­ti­on Con­fe­rence (CAR­DIS 2014).
  • PC co-chair of In­ter­na­tio­nal Work­shop on Light­weight Cryp­to­gra­phy for Se­cu­ri­ty & Pri­va­cy (Light­Sec 2015).
  • PC co-chair of Cryp­to­gra­phic Hard­ware and Em­bed­ded Sys­tems (CHES 2020).
  • Steering Committee Member of CHES, since 2019.
  • Steering Committee Member of CARDIS, since 2014.
  • As­so­cia­te Edi­tor of In­ter­na­tio­nal Jour­nal of Ap­p­lied Cryp­to­gra­phy, 2011-2020 (IJACT).
  • As­so­cia­te Edi­tor of IEEE Tran­sac­tions on Emer­ging To­pics in Com­pu­ting, 2019-2021 (IEEE-TETC).
  • As­so­cia­te Edi­tor of Jour­nal of Cryp­to­gra­phic En­gi­nee­ring, 2019-2022 (JCEN).

Selec­ted Talks

  • Sta­tis­ti­cal Tools Fla­vor Si­de-Chan­nel Col­li­si­on At­tacks, EU­RO­CRYPT 2012, April 17, Cam­bridge, UK. (talk)
  • Brea­king the Bit­stream De­cryp­ti­on of FPGAs, in­vi­ted talk at ECRYPT II Sum­mer School: Chal­len­ges in Se­cu­ri­ty En­gi­nee­ring, 2012, Sep­tem­ber 5, Bo­chum, Ger­ma­ny.
  • How Far Should Theo­ry Be from Prac­tice? Eva­lua­ti­on of a Coun­ter­me­a­su­re, CHES 2012, Sep­tem­ber 10, Leu­ven, Bel­gi­um.
  • On the Sim­pli­ci­ty of Con­ver­ting Le­a­ka­ges from Mul­ti­va­ria­te to Uni­va­ria­te, CHES 2013, Au­gust 21, Santa Bar­ba­ra, US.
  • Al­te­ra vs. Xi­l­inx which one keeps your de­sign hi­d­den? rump ses­si­on CHES 2013, Au­gust 22, Santa Bar­ba­ra, US.
  • Si­de-Chan­nel Coun­ter­me­a­su­res for Hard­ware: is There a Light at the End of the Tun­nel? in­vi­ted talk at Worces­ter Po­ly­tech­nic In­sti­tu­te, 2013, Sep­tem­ber 11, Worces­ter, US.
  • Eva­lua­ti­on of Si­de-Chan­nel Le­a­ka­ges through Sta­tis­ti­cal Mo­ments in­vi­ted talk at Bosch GmbH, 2014, March 13, Stutt­gart, Ger­ma­ny.
  • Si­de-Chan­nel Le­a­ka­ge through Sta­tic Power Should We Care about in Prac­tice? in­vi­ted talk at NXP Se­mi­con­duc­tors, 2014, April 22, Ham­burg, Ger­ma­ny (+ CHES 2014, Sep­tem­ber 26, Busan, South Korea).
  • Early Pro­pa­ga­ti­on and Im­ba­lan­ced Rou­ting, How to Di­mi­nish in FPGAs, CHES 2014, Sep­tem­ber 26, Busan, South Korea.
  • Phy­si­cal At­tacks, extrac­ting the secrets from cryp­to­gra­phic de­vices, in­vi­ted talk at Bau­haus-Uni­ver­si­tät Wei­mar, 2015, Ja­nu­a­ry 22, Wei­mar, Ger­ma­ny.
  • Si­de-Chan­nel Se­cu­ri­ty Ana­ly­sis of Ul­tra-Low-Power FRAM-ba­sed MCUs, CO­SA­DE 2015, April 14, Ber­lin, Ger­ma­ny.
  • Hiding Hig­her-Or­der Le­a­ka­ges in Hard­ware in­vi­ted talk at TI day, KU Leu­ven, Bel­gi­um.
  • Le­a­ka­ge As­sess­ment Me­tho­do­lo­gy – a clear road­map for si­de-chan­nel eva­lua­ti­ons, in­vi­ted talk at Sharif Uni­ver­si­ty of Tech­no­lo­gy, 2015, Au­gust 29, Tehr­an, Iran.
  • Im­pro­ved Si­de-Chan­nel Ana­ly­sis At­tacks on Xi­l­inx Bit­stream En­cryp­ti­on of 5, 6, and 7 Se­ries, CO­SA­DE 2016, April 14, Graz, Aus­tria.
  • Mas­king as a Si­de-Chan­nel Coun­ter­me­a­su­re in Hard­ware, in­vi­ted tu­to­ri­al at ISCISC 2016, Sep­tem­ber 6, Tehr­an, Iran.
  • Mo­ments-Cor­re­la­ting DPA, CCS 2016 Work­shops (TIS), Oc­to­ber 24, Vi­en­na, Aus­tria.
  • Si­de-Chan­nel Ana­ly­sis Pro­tec­tion and Low-La­ten­cy in Ac­tion – case study of PRIN­CE and Mi­do­ri, ASI­A­CRYPT 2016, De­cem­ber 07, Hanio, Viet­nam. (talk)
  • Bit-Sli­ding: A Ge­ne­ric Tech­ni­que for Bit-Se­ri­al Im­ple­men­ta­ti­ons of SPN-ba­sed Pri­mi­ti­ves, CHES 2017, Sep­tem­ber 28, Tai­pei, Tai­wan. (talk)
  • The First Tho­rough Si­de-Chan­nel Hard­ware Tro­jan, ASI­A­CRYPT 2017, De­cem­ber 05, Hong Kong, China. (talk) + at Theo­ry of Im­ple­men­ta­ti­on Se­cu­ri­ty (TIS) Work­shop 2018, Ja­nu­a­ry 09, Zu­rich, Swit­z­er­land
  • Ex­plo­ring the Ef­fect of De­vice Aging on Sta­tic Power Ana­ly­sis At­tacks, CHES 2019, Au­gust 28, At­lan­ta, USA. (talk)
  • How to Apply Thres­hold Im­ple­men­ta­ti­on to any PUF Pri­mi­ti­ve, in­vi­ted talk at Theo­ry of Im­ple­men­ta­ti­on Se­cu­ri­ty (TIS) Work­shop 2019, No­vem­ber 11, Lon­don, Eng­land
  • Threshold Implementation and Leakage Assessment, invited talk at Qualcomm, December 14, 2020
  • Tools for Verification and Automatic Generation of Secure Hardware Circuits, invited talk at National Institute for Standard and Technology, USA, March 10, 2021
  • Verification and Automatic Generation of Masked Hardware Designs, invited talk at Worcester Polytechnic Institute, USA, November 10, 2021
  • Hardware Masking. Past, Present, and the Future, invited talk at Microsoft, December 8, 2021
  •  Automated Generation of Masked Hardware, CHES 2022, September 19, Leuven, Belgium. (talk)

Cur­rent PhDs

Joint Su­per­vi­si­on

Fi­nis­hed PhDs

Funded DFG Pro­jects

  • NaS­CA- Na­no-Sca­le Si­de-Chan­nel Ana­ly­sis: Phy­si­cal Se­cu­ri­ty for Next-Ge­ne­ra­ti­on CMOS ICs (DFG 2016-2020)
  • Green­Sec- Se­cu­ri­ty for In­ter­net of Things with Low En­er­gy and Low Power Con­sump­ti­on (DFG 2018-2021)
  • SuC­CESS- Sym­me­triC Ci­phEr de­sign with in­herent phy­Si­cal Se­cu­ri­ty (DFG 2019-2022)
  • Aged but Fit- Long Las­ting Se­cu­ri­ty for Trusted Plat­forms (DFG 2020-2022)
  • SAU­BER – phy­Si­cAl­ly se­cU­re re­con­fi­gura­BlE plat­foRm (DFG 2020-2023)
  • SecFS­ha­re – Se­cu­re Sharing of FPGAs in Clouds (DFG 2021-2023)

Funded EU Pro­ject(s)

  • enCRYPTON – Twinning towards excellence for Privacy Enhancing Technologies leveraging Homomorphic Encryption (HORIZON-CSA 2022-2025)

Funded BMBF Pro­jects

  • Ve­ri­Sec- Com­pu­ter-As­sis­ted In­te­gra­ti­on and Ve­ri­fi­ca­ti­on of Mas­king in Cryp­to­gra­phic Im­ple­men­ta­ti­ons (BMBF 2017-2020)
  • Sys­Kit- A De­ve­lop­ment Tool for Se­cu­re Com­mu­ni­ca­ti­ons in In­dus­try 4.0 (BMBF 2017-2020)
  • mIND­FUL – In­tru­si­on De­tec­tion in In­dus­try 4.0 via Fu­si­on of Phy­si­cal Chan­nels using Ar­ti­fi­ci­al In­tel­li­gence (BMBF 2020-2023)
  • KOSEF – Cost-optimized and Effective Protection against Electromagnetic Fault Injection to Ensure Data and Operational Reliability in loT Systems. (BMBF 2022-2025)
  • DevToSCA – Developer-Centric Tools for Side-Channel Analysis (BMBF 2022-2025)
  • ProPair – Context-based Trust Initialization of Telemedicine Micro Devices (BMBF 2022-2025)

Teaching

  • 212415: MSc Lab Course “Side-Channel Analysis Attacks”
  • 211034: MSc Lecture “Physical Attacks and Countermeasures”
  • 141304: BSc Lecture “Digital Circuit Design” (Digitaltechnik)
  • 212126: BSc Seminar “Implementation Security”
  • 212126: MSc Seminar “Implementation Security”

Publications

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